cy29774 Cypress Semiconductor Corporation., cy29774 Datasheet - Page 3

• Manufacturer Part Number: cy29774
• Description: 2.5v Or 3.3v, 125-mhz, 14 Output Zero Delay Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Table 1. Frequency Table
Table 2. Function Table (configuration controls)
Table 3. Function Table (Bank A, B and C)
Table 4. Function Table (FB_OUT)
Document #: 38-07479 Rev. **
TCLK_SEL
CLK_STP#
VCO_SEL
Feedback Output
VCO_SEL
PLL_EN
MR#/OE
Control
VCO_SEL
0
0
1
1
Divider
0
0
0
0
1
1
1
1
12
16
24
32
48
8
Default
SELA
0
0
1
1
1
0
1
0
1
FB_SEL1
Input Clock * 12
Input Clock * 16
Input Clock * 24
Input Clock * 32
Input Clock * 48
Input Clock * 8
0
0
1
1
0
0
1
1
device. During reset/output disable the PLL feedback
loop is open and the VCO running at its minimum
power-on reset (POR) circuitry during power-up.
QA, QB, and QC outputs disabled in LOW state.
Outputs disabled (three-state) and reset of the
VCO
frequency. The device is reset by the internal
Bypass mode, PLL disabled. The input clock
FB_OUT is not affected by CLK_STP#.
QA(4:0)
VCO 2 (high input frequency range)
connects to the output dividers
16
4
8
8
FB_SEL0
0
1
0
1
0
1
0
1
TCLK0
0
Input Frequency Range
6.25 MHz to 15.625 MHz
12.5 MHz to 31.25 MHz
16.6 MHz to 41.6 MHz
SELB
8.3 MHz to 20.8 MHz
4.2 MHz to 10.4 MHz
25 MHz to 62.5 MHz
0
1
0
1
(AVDD = 3.3V)
FB_OUT
QB(4:0)
16
12
24
16
32
24
48
8
16
4
8
8
VCO 4 (low input frequency range)
connects to the output dividers
PLL enabled. The VCO output
Input Frequency Range
SELC
16.6 MHz to 33.3 MHz
6.25 MHz to 12.5 MHz
8.3 MHz to 16.6 MHz
12.5 MHz to 25 MHz
Outputs enabled
Outputs enabled
4.2 MHz to 8.3 MHz
0
1
0
1
25 MHz to 50 MHz
(AVDD = 2.5V)
TCLK1
1
CY29774
QC(3:0)
Page 3 of 9
12
16
24
8
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