cy29774 Cypress Semiconductor Corporation., cy29774 Datasheet

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cy29774

Manufacturer Part Number
cy29774
Description
2.5v Or 3.3v, 125-mhz, 14 Output Zero Delay Buffer
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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774
Features
Description
The CY29774 is a low-voltage high-performance 125-MHz
PLL-based zero delay buffer designed for high-speed clock
distribution applications.
Cypress Semiconductor Corporation
Document #: 38-07479 Rev. **
• Output frequency range: 8.3 MHz to 125 MHz
• Input frequency range: 4.2 MHz to 62.5 MHz
• 2.5V or 3.3V operation
• Split 2.5V/3.3V outputs
• 14 Clock outputs: Drive up to 28 clock lines
• 1 Feedback clock output
• 2 LVCMOS reference clock inputs
• 150 ps max output-output skew
• PLL bypass mode
• Spread Aware™
• Output enable/disable
• Pin compatible with MPC9774
• Industrial temperature range: –40°C to +85°C
• 52-Pin 1.0-mm TQFP package
Block Diagram
TC LK _ S EL
V C O _S E L
C LK _ S TP #
F B _S E L(1,0)
P L L_ E N
M R #/O E
T C LK 1
TC LK 0
S E L A
S E LC
FB _IN
S E LB
5 00M H z
20 0 -
P L L
2
4
2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer
2 / 4
2 / 4
4 / 6
4 / 6 / 8 / 12
3901 North First Street
S TO P
S T O P
S T O P
C L K
C L K
C L K
F B _O U T
Q B 3
Q B 4
Q C 0
Q C 1
Q C 2
Q C 3
Q A 0
Q A 1
Q A 2
Q A 3
Q A 4
Q B 0
Q B 1
Q B 2
The CY29774 features two reference clock inputs and pro-
vides 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs.
Bank A and Bank B divide the VCO output by 4 or 8 while Bank
C divides by 8 or 12 per SEL(A:C) settings, see Functional
Table. These dividers allow output to input ratios of 6:1, 4:1,
3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each LVCMOS compatible out-
put can drive 50
lines. For series terminated transmission lines, each output
can drive one or two traces giving the device an effective
fanout of 1:28.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 8.3 MHz to 125 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback di-
vider, see Frequency Table.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Pin Configuration
CLK_STP#
TCLK_SEL
MR#/OE
PLL_EN
TCLK0
TCLK1
AVDD
SELC
SELB
SELA
San Jose
VDD
VSS
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
52 51 50 49 48 47 46 45 44 43 42 41 40
14 15 16 17 18 19 20 21 22 23 24 25 26
series or parallel terminated transmission
CY29774
CA 95134
Revised April 28, 2003
39
38
37
36
35
34
33
32
31
30
29
28
27
CY29774
408-943-2600
VSS
QB1
VDDQB
QB2
VSS
QB3
VDDQB
QB4
FB_IN
VSS
FB_OUT
VDDFB
NC
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cy29774 Summary of contents

Page 1

... Cypress Semiconductor Corporation Document #: 38-07479 Rev. ** 2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer The CY29774 features two reference clock inputs and pro- vides 14 outputs partitioned in 3 banks and 4 outputs. Bank A and Bank B divide the VCO output while Bank C divides per SEL(A:C) settings, see Functional Table ...

Page 2

... Power supply for bank B output clocks VDD 2.5V or 3.3V Power supply for bank C output clocks VDD 2.5V or 3.3V Power supply for feedback output clock VDD 2.5V or 3.3V Power supply for PLL VDD 2.5V or 3.3V Power supply for core and inputs Ground Analog Ground Ground Common Ground No Connection CY29774 Description [2,3] [2,3] [2,3] [2,3] [2,3] [2,3] Page [+] Feedback ...

Page 3

... CY29774 Input Frequency Range (AVDD = 2.5V) 25 MHz to 50 MHz 16.6 MHz to 33.3 MHz 12.5 MHz to 25 MHz 8.3 MHz to 16.6 MHz 6.25 MHz to 12.5 MHz 4.2 MHz to 8.3 MHz 1 TCLK1 VCO 4 (low input frequency range) PLL enabled. The VCO output connects to the output dividers ...

Page 4

... T = –40°C to +85°C) A Condition LVCMOS LVCMOS – Alternatively, each output drives up to two 50 TT CY29774 Min. Max. Unit –0.3 5.5 V 2.375 3.465 V –0 0 –0 0 – 200 – ...

Page 5

... Output 16 Output 24 Output 0.7V to 1.8V TCLK to FB_IN, does not include jitter Skew within Bank Banks at same frequency Banks at different frequency Same frequency Multiple frequencies . Parameters are guaranteed by characterization and are not 100% tested. TT CY29774 Min. Typ. Max. Unit – – – – ...

Page 6

... TCLK to FB_IN, same does not include jitter Skew within Bank Banks at same voltage, same frequency Banks at same voltage, different frequency Banks at different voltage Same frequency Multiple frequencies I/O at same V DD CY29774 Min. Typ. Max. Unit 200 – 500 MHz 25 – 62.5 MHz 16.6 – ...

Page 7

... ohm ohm ohm T VTT = 3. 100% Figure 3. Output Duty Cycle (DC) t SK(O) Figure 4. Output-to-Output Skew, t sk(O) CY29774 ohm T VTT DD DD/2 ND VDD VDD/2 GND VDD VDD/2 GND Page [+] Feedback ...

Page 8

... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Type Industrial, – +85 C Industrial, – Package Drawing and Dimension CY29774 Product Flow 51-85158-** Page [+] Feedback ...

Page 9

... Document History Page Document Title:CY29774 2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer Document #: 38-07479 Issue Rev. ECN No. Date ** 125954 05/01/03 Document #: 38-07479 Rev. ** Orig. of Description of Change Change RGL New Data Sheet CY29774 Page [+] Feedback ...

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