cy29658 Cypress Semiconductor Corporation., cy29658 Datasheet - Page 2

• Manufacturer Part Number: cy29658
• Description: 2.5v Or 3.3v 200-mhz 10-output Zero Delay Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07478 Rev. **
Pin Description
Table 1. Frequency Table
Table 2. Function Table
6
7
10, 12, 14,
16, 18, 20,
22, 24, 26, 28
30
2
5
4
3
32
11, 15, 19,
23, 31
1
27
8
9, 13, 17, 21,
25, 29
Notes:
1.
2.
3.
Feedback Output Divider
VCO_SEL
PU = Internal pull-up, PD = Internal pull-down.
A 0.1- F bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQ power supply pin.
BYPASS#
Pin
MR/OE#
PLL_EN
Control
PECL_CLK
PECL_CLK#
Q(9:0)
FB_OUT
FB_IN
MR/OE#
PLL_EN
BYPASS#
VCO_SEL
VDDQ
AVDD
VDD
AVSS
VSS
2
4
Name
[1]
Default
1
1
1
0
Input Clock * 2
Input Clock * 4
Supply
Supply
Supply
Supply
Supply
I, PU
I, PU
I, PU
I, PD
I, PU
I, PU
I, PU
I/O
O
O
Bypass mode, PLL disabled. The input
clock connects to the output dividers
Bypass mode with PLL and output
dividers bypassed. The input clock
connects to the outputs.
Outputs enabled
VCO
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVPECL
LVPECL
Ground
Ground
Type
VDD
VDD
VDD
VCO
LVPECL reference clock input.
LVPECL reference clock input. Pull-up to VDD/2.
Clock output.
Feedback clock output. Connect to FB_IN for normal operation.
Feedback clock input. Connect to FB_OUT for normal operation. This
input should be at the same voltage rail as input reference clock. See
Table 1.
Output enable/disable input. See Table 2.
PLL enable/disable input. See Table 2.
PLL and output divider bypass select input. See Table 2.
VCO divider select input. See Table 2.
2.5V or 3.3V power supply for output clocks.
2.5V or 3.3V power supply for PLL.
2.5V or 3.3V power supply for core and inputs.
Analog ground.
Common ground.
0
100 MHz to 200 MHz
50 MHz to 125 MHz
1
Input Frequency Range
(AVDD = 3.3V)
PLL enabled. The VCO output connects to the
output dividers
Selects the output dividers
Outputs disabled (three-state), VCO running at
its minimum frequency
Description
[2,3]
100 MHz to 200 MHz
50 MHz to 100 MHz
Input Frequency Range
VCO
1
(AVDD = 2.5V)
[2,3]
2
[2,3]
CY29658
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