cy2xp21 Cypress Semiconductor Corporation., cy2xp21 Datasheet - Page 5

• Manufacturer Part Number: cy2xp21
• Description: 125 Mhz Lvpecl Clock Generator
• Manufacturer: Cypress Semiconductor Corporation.

Application Information
Power Supply Filtering Techniques
As in any high speed analog circuitry, noise at the power supply
pins can degrade performance. To achieve optimum jitter perfor-
mance, use good power supply isolation practices.
trates a typical filtering scheme. Since all the current flows
through pin 1, the resistance and inductance between this pin
and the supply is minimized. A 0.01 or 0.1 µF ceramic chip
capacitor is also located close to this pin to provide a short and
low impedance AC path to ground. A 1 to 10 µF ceramic or
tantalum capacitor is located in the general vicinity of this device
and may be shared with other devices.
Figure 8. Power Supply Filtering
Termination for LVPECL Output
The CY2XP21 implements its LVPECL driver with a current
steering design. For proper operation, it requires a 50 ohm dc
termination on each of the two output signals. For 3.3V
operation, this data sheet specifies output levels for termination
to V
V
that it is also possible to terminate with 50 ohms to ground (V
but the high and low signal levels differ from the data sheet
values. Termination resistors are best located close to the desti-
nation device. To avoid reflections, trace characteristic
impedance (Z
Figure 9
Document #: 001-52849 Rev. *B
DD
DD
= 2.5V operation, or it can be terminated to V
–2.0V. This same termination voltage can also be used for
shows a standard termination scheme.
(Pin 1)
0
(Pin 8)
) should match the termination impedance.
V DD
V DD
0.1μF
0.01 µF
3.3V
10µ F
DD
PRELIMINARY
Figure 8
-1.5V. Note
illus-
SS
),
Figure 9. LVPECL Output Termination
Crystal Interface
The CY2XP21 is characterized with 18 pF parallel resonant
crystals. The capacitor values shown in
mined using a 25 MHz 18 pF parallel resonant crystal and are
chosen to minimize the ppm error. Note that the optimal values
for C1 and C2 depend on the parasitic trace capacitance and are
thus layout dependent.
Figure 10. Crystal Input Interface
Board Layout and NC Pin
Pin 5 (NC) does not perform any function on the CY2XP21.
Although not used electrically, it is very useful for heat dissi-
pation. For this reason, users are advised to connect pin 5 to
either a V
tance of the board / package combination, thus reducing the die
temperature.
CLK#
CLK
18 pF Parallel
DD
Crystal
or V
X1
SS
plane. This helps to lower the thermal resis-
Z0 = 50Ω
Z0 = 50Ω
30 pF
27 pF
C1
C2
XOUT
XIN
84Ω
125Ω
Device
Figure 10
3.3V
84Ω
125Ω
CY2XP21
Page 5 of 7
are deter-
IN
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