cy2xp21 Cypress Semiconductor Corporation., cy2xp21 Datasheet

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cy2xp21

Manufacturer Part Number
cy2xp21
Description
125 Mhz Lvpecl Clock Generator
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Part Number:
cy2xp21ZXI
Manufacturer:
Cypress
Quantity:
200
Features
Table 1. Pin Definition - 8-Pin TSSOP
Cypress Semiconductor Corporation
Document #: 001-52849 Rev. *B
Pinouts
Pin Number
1, 8
2
3, 4
5
6,7
One LVPECL Output Pair
Output Frequency: 112 MHz to 140 MHz
External Crystal Frequency: 22.4 MHz to 28 MHz
Low RMS Phase Jitter at 125 MHz, using 25 MHz Crystal
(1.875 MHz to 20 MHz): 0.4 ps (Typical)
Pb-free 8-Pin TSSOP Package
Supply Voltage: 3.3V or 2.5V
Commercial and Industrial Temperature Ranges
Logic Block Diagram
VDD
VSS
XOUT, XIN
NC
CLK#, CLK
External
Pin Name
Crystal
Power
Power
XTAL output and input
LVPECL output
XOUT
XIN
XOUT
I/O Type
OSCILLATOR
VDD
VSS
CRYSTAL
XIN
Figure 1. Pin Diagram - 8-Pin TSSOP
PRELIMINARY
198 Champion Court
1
2
3
4
125 MHz LVPECL Clock Generator
3.3V or 2.5V power supply
Ground
Parallel resonant crystal interface
No Connect
Differential clock output
LOW -N OISE
Functional Description
The CY2XP21 is a PLL (Phase Locked Loop) based high
performance clock generator. It is optimized to generate a
125 MHz clock, which is ideal for 10 Gb Ethernet applications. It
also produces an output frequency that is five times the crystal
frequency. It uses Cypress’s low noise VCO technology to
achieve less than 1 ps typical RMS phase jitter. The CY2XP21
has a crystal oscillator interface input and one LVPECL output
pair.
PLL
8
7
6
5
San Jose
VDD
CLK
CLK#
NC
OUTPUT
DIVIDER
,
Description
CA 95134-1709
Revised September 22, 2009
CY2XP21
408-943-2600
CLK
CLK#
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cy2xp21 Summary of contents

Page 1

... MHz clock, which is ideal for 10 Gb Ethernet applications. It also produces an output frequency that is five times the crystal frequency. It uses Cypress’s low noise VCO technology to achieve less than 1 ps typical RMS phase jitter. The CY2XP21 has a crystal oscillator interface input and one LVPECL output pair. ...

Page 2

... R = 50Ω TERM DD V – 2. 3.3V or 2.5V 50Ω TERM V – 2. 2.5V 50Ω – DD TERM DD 1.5V CY2XP21 Output Frequency (MHz) 125 133 Min Max Unit –0.5 4.4 V –0 0 °C –65 150 °C – 135 2000 – V V–0 °C/W ...

Page 3

... Time for CLK to reach valid frequency measured from the time (min [4] Description Figure 2. 3.3V Output Load AC Test Circuit 50Ω V CLK DD LVPECL Z = 50Ω CLK -1.3V +/- 0.165V CY2XP21 Min Typ Max – 1.2 – – – 4.5 – Min Typ Max 112 – 140 – 0.5 1.0 – ...

Page 4

... CLK Figure 6. RMS Phase Jitter Phase noise Phase noise mask Offset Frequency f2 f1 RMS Jitter = Area Under the Masked Phase Noise Plot Figure 7. Output Duty Cycle PERIOD CY2XP21 SCOPE 50Ω 50Ω )/2 OCM 20 ...

Page 5

... Crystal -1.5V. Note Board Layout and NC Pin Pin 5 (NC) does not perform any function on the CY2XP21. Although not used electrically very useful for heat dissi- pation. For this reason, users are advised to connect pin 5 to either tance of the board / package combination, thus reducing the die temperature ...

Page 6

... PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. 0.25[0.010] 1.10[0.043] MAX. BSC GAUGE 0°-8° PLANE 0.076[0.003] SEATING PLANE CY2XP21 Product Flow Commercial, 0°C to 70°C Commercial, 0°C to 70°C Industrial, -40°C to 85°C Industrial, -40°C to 85°C MAX. 0.50[0.020] 0.09[[0.003] 0.70[0.027] 0.20[0.008] ...

Page 7

... Document History Page Document Title: CY2XP21 125 MHz LVPECL Clock Generator Document Number: 001-52849 Submission REV. ECN NO. Date ** 2700242 04/30/09 *A 2718898 06/15/09 *B 2767298 09/22/09 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...

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