fs7140 ON Semiconductor, fs7140 Datasheet - Page 7

• Manufacturer Part Number: fs7140
• Description: Programmable Phase- Locked Loop Clock Generator
• Manufacturer: ON Semiconductor

N
N
N
it allows the VCO to be operated in a narrower range of
speeds compared to the variety of output clock speeds that
the device is required to generate. Second, the extra integer
in the denominator permits more flexibility in the
programming of the loop for many applications where
frequencies must be achieved exactly.
Note that a nominal 50/50 duty factor is always preserved
(even for selections which have an odd modulus).
Crystal Oscillator
oscillator. The crystal is operated in parallel resonant mode.
Internal load capacitance is provided for the crystal. While
a recommended load capacitance for the crystal is specified,
crystals for other standard load capacitances may be used if
great precision of the reference frequency (100 ppm or less)
is not required.
Reference Divider Source MUX
chosen to be the device crystal oscillator or the REF pin by
the REFDSRC bit.
connect XIN to VSS. Do not connect to XOUT.
floating or connected to V
Feedback Divider Source MUX
selected to be either the output of the post divider or the
output of the VCO by the FBKDSRC bit.
is used. Use the output of the post divider only where a
deterministic phase relationship between the output clock
and reference clock are desired (line−locked mode, for
example).
P2
PX
PX
The moduli of the individual dividers are denoted as N
The post divider performs several useful functions. First,
See Table 12 for additional information.
The FS7140 is equipped with a Pierce−type crystal
The source of frequency for the reference divider can be
When not using the crystal oscillator, it is preferred to
When not using the REF input, it is preferred to leave it
The source of frequency for the feedback divider may be
Ordinarily, for frequency synthesis, the output of the VCO
.
and N
= N
P1
P3
x N
, and together they make up the array modulus
P2
x N
P3
DD
.
Figure 2. Post Divider
http://onsemi.com
P1
,
7
Device Shutdown
desired, when it is not active. SHUT1 disables most
externally observable device functions. SHUT2 reduces
device quiescent current to absolute minimum values.
Normally, both bits should be set or cleared together.
SHUT1 or SHUT2.
Differential Output Stage
pseudo−ECL (PECL) signals. The desired output interface
is chosen via the programming registers.
terminated using a Thévenin termination. The output stage
can only sink current in the PECL mode, and the amount of
sink current is set by a programming resistor on the
LOCK/IPRG pin. The ratio of output sink current to IPRG
current is 13:1. Source current for the CLKx pins is provided
by the pull−up resistors that are part of the Thévenin
termination.
Example
buffer right next to the FS7140.
•
•
•
•
Then:
R1 (from CLKP and CLKN output to VDD) =
R2 (from CLKP and CLKN output to GND) =
Rprgm (from VDD to IPRG pin) =
Two bits are provided to effect shutdown of the device if
Serial communications capability is not disabled by either
The differential output stage supports both CMOS and
If a PECL interface is used, the transmission line is usually
Assume that it is desired to connect a PECL−type fanout
Further assume:
R
75 * 3.3 / 2.4 =
103 ohms
R
75 * 3.3 / (3.3 − 2.4) =
275 ohms
26 * (V
26 * (3.3 * 75) / (2.4 − 1.6) / 3 =
2.68 Kohms
V
Desired V
Desired V
Equivalent R
LOAD
LOAD
DD
= 3.3 V
DD
* V
* V
HI
LO
* R
DD
DD
= 2.4 V
LOAD
= 1.6 V
LOAD
/ V
/ (V
HI
DD
= 75 ohms
) / (V
=
− V
HI
HI
) =
− V
LO
) / 3 =