fs7140 ON Semiconductor, fs7140 Datasheet - Page 5

• Manufacturer Part Number: fs7140
• Description: Programmable Phase- Locked Loop Clock Generator
• Manufacturer: ON Semiconductor

2. Unless otherwise stated, V
CLOCK OUTPUTS, CMOS MODE (CLKN, CLKP)
CLOCK OUTPUTS, PECL MODE (CLKN, CLKP)
OVERALL
REFERENCE FREQUENCY INPUT (REF)
SYNC CONTROL INPUT (SYNC)
CLOCK OUTPUT (CLKN, CLKP)
Table 4. DC ELECTRICAL SPECIFICATIONS
1. Unless otherwise stated, V
Table 5. AC TIMING SPECIFICATIONS
Low−level output sink current
IPRG bias voltage
IPRG bias current
Sink current to IPRG current ratio
Tristate output current
Output frequency*
VCO frequency*
CMOS mode rise time*
CMOS mode fall time*
PECL mode rise time*
PECL mode fall time*
Input frequency
Reference high time
Reference low time
Sync high time
Sync low time
Duty cycle (CMOS mode)*
Duty cycle (PECL mode)*
Jitter, long term (s
Jitter, period (peak−peak)*
with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization
data are ± 3s from typical.
with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characteriza-
tion data are ± 3s from typical. Negative currents indicate flows out of the device.
Parameter
Parameter
y
(t))*
DD
DD
= 3.3 V ± 10%, no load on any output, and ambient temperature range T
= 3.3 V ± 10%, no load on any output, and ambient temperature range T
Symbol
t
t
f
SYNCH
t
SYNCL
t
o(max)
F
f
t
REHF
t
REFL
j(DP)
VCO
j(LT)
REF
t
t
t
t
r
f
r
f
Symbol
V
I
IPRG
I
IPRG
OL
I
Z
(Note 2)
CMOS outputs
PECL outputs
C
C
C
C
For orderly CLK stop/start
For orderly CLK stop/start
Measured at 1.4 V
Measured at zero crossings of
(V
For valid programming solutions. Long-term (or cumulative) jitter specified is
RMS position error of any edge compared with an ideal clock generated from
the same reference frequency. It is measured with a time interval analyzer us-
ing a 500 microsecond window, using statistics gathered over 1000 samples.
FREF/NREF > 1000 kHz
FREF/NREF ^ 500 kHz
FREF/NREF ^ 250 kHz
FREF/NREF ^ 125 kHz
FREF/NREF ^ 62.5 kHz
FREF/NREF ^ 31.5 kHz
40 MHz < VCO frequency < 100 MHz
VCO frequency > 100 MHz
L
L
L
L
CLKP
= 7 pF
= 7 pF
= 7 pF; R
= 7 pF; R
V
V
when a resistor is connected from
VDD to IPRG
I
(Note 1)
IPRG
O
IPRG
− V
= 0.4 V
Conditions/Description
http://onsemi.com
− (V
CLKN
Conditions/Description
will be clamped to this level
L
L
= 65 ohm
= 65 ohm
VDD
)
− V
5
IPRG
) / R
SET
Min
Min
−10
40
0
0
3
3
3
3
A
A
= 0°C to 70°C. Parameters denoted
= 0°C to 70°C. Parameters denoted
V
Typ
−35
Typ
100
190
240
300
DD
13
50
50
25
50
75
50
1
1
1
1
/3
Max
Max
150
300
400
3.5
10
80
Units
Units
T
MHz
MHz
MHz
mA
mA
mA
ns
ns
ns
ns
ns
ns
CLK
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
%
V