fs7140 ON Semiconductor, fs7140 Datasheet - Page 6

• Manufacturer Part Number: fs7140
• Description: Programmable Phase- Locked Loop Clock Generator
• Manufacturer: ON Semiconductor

3. Unless otherwise stated, V
Phase Locked Loop (PLL)
architecture. The PLL consists of a reference divider, a
phase−frequency detector (PFD), a charge pump, an internal
loop filter, a voltage−controlled oscillator (VCO), a
feedback divider, and a post divider.
on−board crystal oscillator or an external frequency source),
is first reduced by the reference divider. The integer value
that the frequency is divided by is called the modulus and is
denoted as NR for the reference divider. This divided
reference is then fed into the PFD.
feedback divider (the modulus is denoted by NF).
the divided reference frequency and the divided VCO
frequency appearing at the inputs of the PFD are equal. The
input/output relationship between the reference frequency
and the VCO frequency is then:
Table 6. SERIAL INTERFACE TIMING SPECIFICATIONS
Clock frequency
Bus free time between STOP and START
Set−up time, START (repeated)
Hold time, START
Set−up time, data input
Hold time, data input
Output data valid from clock
Rise time, data and clock
Fall time, data and clock
High time, clock
Low time, clock
Set−up time, STOP
The PLL is a standard phase− and frequency−locked loop
The reference frequency (generated by either the
The VCO frequency is fed back to the PFD through the
The PFD will drive the VCO up or down in frequency until
This basic PLL equation can be rewritten as
with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization
data are ± 3s from typical.
Parameter
f
VCO
f
VCO
N
+ f
F
DD
+
REF
= 3.3 V ± 10%, no load on any output, and ambient temperature range T
f
N
REF
R
N
N
R
F
FUNCTIONAL BLOCK DIAGRAM
Symbol
T
T
t
t
t
su:STO
hd:STA
hd:DAT
su:STA
su:DAT
f
t
SCL
BUF
t
t
t
http://onsemi.com
AA
t
LO
t
HI
R
F
(Note 3)
6
Conditions/Description
dividers) follows the PLL and the final equation for device
output frequency is:
Reference Divider
divider accepts the output of either the crystal oscillator
circuit or an external reference frequency. The reference
divider is a 12 bit divider, and can be programmed for any
modulus from 1 to 4095 (divide by 1 not available on date
codes prior to 0108).
Feedback Divider
(also called dual−modulus prescaler) technique. It permits
division by any integer value between 12 and 16383. Simply
program the FBKDIV register with the binary equivalent of
the desired modulus. Selected moduli below 12 are also
permitted. Moduli of: 4, 5, 8, 9, and 10 are also allowed (4
and 5 are not available on date codes prior to 0108).
Post Divider
programmable dividers, as shown in Figure 2.
A post divider (actually a series combination of three post
The reference divider is designed for low phase jitter. The
The feedback divider is based on a dual−modulus divider
The post divider consists of three individually
SDA, SCL
SDA, SCL
SDA
SDA
SCL
SCL
SCL
f
CLK
+ f
REF
A
= 0°C to 70°C. Parameters denoted
1300
1300
Min
600
600
100
600
600
N
N
0
0
R
F
Fast Mode
N
1
Px
Max
400
900
300
300
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns