MX26LV160AT Macronix International, MX26LV160AT Datasheet - Page 11

• Manufacturer Part Number: MX26LV160AT
• Description: 16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE 3V ONLY BOOT SECTOR HIGH SPEED eLiteFlashTM MEMORY
• Manufacturer: Macronix International

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nal reset operation is complete, which requires a time of
tREADY (during Embedded Algorithms). The system can
thus monitor RY/BY# to determine whether the reset
operation is complete. If RESET# is asserted when a
program or erase operation is completed within a time of
tREADY (not during Embedded Algorithms). The sys-
tem can read data tRH after the RESET# pin returns to
VIH.
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 21 for the timing diagram.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.
SILICON-ID READ COMMAND
High speed Flash memories are intended for use in ap-
plications where the local CPU alters memory contents.
As such, manufacturer and device codes must be ac-
cessible while the device resides in the target system.
PROM programmers typically access signature codes
by raising A9 to a high voltage (VID). However, multi-
plexing high voltage onto address lines is not generally
desired system design practice.
The MX26LV160AT/AB contains a Silicon-ID-Read op-
eration to supple traditional PROM programming meth-
odology. The operation is initiated by writing the read
silicon ID command sequence into the command regis-
ter.
SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
P/N:PM1123
MX26LV160AT/AB
11
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H or
sector erase command 30H.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Au-
tomatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero
pattern, a self-timed chip erase and verify begin. The
erase and verify operations are completed when the data
on Q7 is "1" at which time the device returns to the
Read mode. The system is not required to provide any
control or timing during these operations.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required).
If the Erase operation was unsuccessful, the data on
Q5 is "1" (see Table 7), indicating the erase operation
exceed internal timing limit.
The automatic erase begins on the rising edge of the
last WE# or CE# pulse, whichever happens first in the
command sequence and terminates when the data on
Q7 is "1" at which time the device returns to the Read
mode, or the data on Q6 stops toggling for two consecu-
tive read cycles at which time the device returns to the
Read mode.
REV. 1.1, NOV. 18, 2004