MX25L1605 Macronix International, MX25L1605 Datasheet - Page 15

• Manufacturer Part Number: MX25L1605
• Description: 16M-BIT [x 1] CMOS SERIAL FLASH
• Manufacturer: Macronix International

MX25L1605
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(12) Enter 4Kbit Mode (EN4K) and Exit 4Kbit Mode (EX4K)
Enter and Exit 4kbit mode (EN4K & EX4K) (see Figure 27 & 28)
EN4K and EX4K will not be executed when the chip is in busy state. Enter 4kbit mode then the read and write command
will be executed on this 4kbit. All read and write command sequence is the same as the normal array. The address of
this 4k bits is: A20~A9=0 and A8~A0 customer defined.
Note 1: Chip erase and WRSR will not be executed in 4kbit mode. During Enter 4Kbit Mode, the following instructions
can be accepted: WREN, WRDI, RDID, RDSR, FAST_READ, READ, SE, PP, DP, RDP, RES, REMS.
Note 2: Chip erase can't erase this 4kbit
About the fail status:
Bit6 of the status register is used to state fail status, bit6=1 means program or erase have been failed. Any new write
command will clear this bit.
(13) Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the
Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the
Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/
Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's
different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low-> sending DP instruction code-> CS# goes high. (see Figure
22)
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and
Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out). When Power-down, the deep
power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP
instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in);
otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before
entering the Deep Power-down mode and reducing the current to ISB2.
(14) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select
(CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-
down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down
mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Se-lect (CS#) must remain High
for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode, the device waits to be selected, so
that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID
Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new deisng, please
use RDID instruction. Even in Deep power-down mode, the RDP, RES, and REMS are also allowed to be executed, only
except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle
in progress.
The sequence is shown as Figure 23,24,25.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if
P/N: PM1168
REV. 1.3, NOV. 06, 2006
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