MX25L1605 Macronix International, MX25L1605 Datasheet

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MX25L1605

Manufacturer Part Number
MX25L1605
Description
16M-BIT [x 1] CMOS SERIAL FLASH
Manufacturer
Macronix International
Datasheet

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FEATURES
GENERAL
• Serial Peripheral Interface (SPI) compatible -- Mode 0
• 16,777,216 x 1 bit structure
• 32 Equal Sectors with 64K byte each
• Single Power Supply Operation
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
• High Performance
• Low Power Consumption
• Minimum 10K erase/program cycle for array
• Minimum 100K erase/program cycle for additional 4Kb
SOFTWARE FEATURES
• Input Data Format
• Auto Erase and Auto Program Algorithm
P/N: PM1168
and Mode 3
- Any sector can be erased
- 2.7 to 3.6 volt for read, erase, and program operations
- Fast access time: 50MHz serial clock (30pF + 1TTL
Load)
- Fast program time: 3ms/page (typical, 256-byte per
page)
- Fast erase time: 1s/sector (typical, 64K-byte per
sector) and 32s/chip (typical)
- Acceleration mode:
- Low active read current: 30mA (max.) at 50MHz
- Low active programming current: 30mA (max.)
- Low active erase current: 38mA (max.)
- Low standby current: 50uA (max.)
- Deep power-down mode 1uA (typical)
- 1-byte Command code
- Program time: 2.4ms/page (typical)
- Erase time: 0.8s/sector (typical) and 25s/chip
(typical)
16M-BIT [x 1] CMOS SERIAL eLiteFlash
1
• Status Register Feature
• Electronic Identification
• Additional 4Kb sector independent from main memory
HARDWARE FEATURES
• SCLK Input
• SI Input
• SO/PO7
• WP#/ACC Pin
• HOLD# pin
• PO0~PO6
• PACKAGE
- Serial Data Output or Parallel mode Data output/input
-
sector
-
page by an internal algorithm that automatically times
the program pulse widths (Any page to be programed
should have page in the erased state first)
-
- RES command, 1-byte Device ID
- REMS command, ADD=00H will output the
manufacturer's ID first and ADD=01H will output device
ID first
for parameter storage to eliminate EEPROM from
system
-
-
-
eration
-
paralled mode, please connect HOLD# pin to VCC dur-
ing parallel mode)
- for parallel mode data output/input
-
Macronix NBit
JEDEC 2-byte Device ID
Serial Data Input
16-pin SOP (300mil)
Automatically programs and verifies data at selected
Serial clock input
Hardware write protection and Program/erase accel-
pause the chip without diselecting the chip (not for
Automatically erases and verifies data at selected
MX25L1605
TM
Memory Family
REV. 1.3, NOV. 06, 2006
TM
MEMORY

Related parts for MX25L1605

MX25L1605 Summary of contents

Page 1

... HOLD# pin - pause the chip without diselecting the chip (not for paralled mode, please connect HOLD# pin to VCC dur- ing parallel mode) • PO0~PO6 - for parallel mode data output/input • PACKAGE - 16-pin SOP (300mil) 1 MX25L1605 TM Memory Family TM MEMORY REV. 1.3, NOV. 06, 2006 ...

Page 2

... GENERAL DESCRIPTION The MX25L1605 is a CMOS 16,777,216 bit serial eLiteFlash TM Memory, which is configured as 2,097,152 x 8 internally. The MX25L1605 features a serial peripheral interface and software protocol allowing operation on a simple 3- wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO) ...

Page 3

... BLOCK DIAGRAM SI CS#, ACC, WP#,HOLD# SCLK P/N: PM1168 Address Generator Memory Array Data Register Y-Decoder SRAM Buffer Mode State HV Logic Machine Generator Clock Generator 3 MX25L1605 Output Sense Amplifier Buffer SO REV. 1.3, NOV. 06, 2006 ...

Page 4

... DATA PROTECTION The MX25L1605 are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences ...

Page 5

... The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0. P/N: PM1168 Protection Area 16Mb None Upper 32nd (Sector 31) Upper sixteenth (two sectors: 30 and 31) Upper eighth (four sectors 31) Upper quarter (eight sectors 31) Upper half (sixteen sectors 31) All All 5 MX25L1605 REV. 1.3, NOV. 06, 2006 ...

Page 6

... AND PROGRAM PERFORMACE". Figure 2. ACCELERATED PROGRAM TIMING DIAGRAM V HH 12V ACC Note: tVHH (VHH Rise and Fall Time) min. 250ns P/N: PM1168 Hold Condition (standard) t VHH 6 MX25L1605 Hold Condition (non-standard VHH REV. 1.3, NOV. 06, 2006 ...

Page 7

... Down) sector) sector) 02 Hex B9 Hex A5 Hex B5 Hex AB Hex AD1 AD2 AD3 Enter Exit the the additional additional 4Kb 4Kb sector sector 7 MX25L1605 READ Fast Read Parallel Mode data) 03 Hex 0B Hex 55 Hex AD1 AD1 AD2 AD2 AD3 AD3 x n bytes Enter and stay in ...

Page 8

... MX25L1605 Address Range 0F0000h 0FFFFFh 0E0000h 0EFFFFh 0D0000h 0DFFFFh 0C0000h 0CFFFFh 0B0000h 0BFFFFh 0A0000h 0AFFFFh 090000h 09FFFFh 080000h 08FFFFh 070000h 07FFFFh 060000h 06FFFFh 050000h 05FFFFh 040000h 04FFFFh 030000h ...

Page 9

... CPOL indicates clock polarity of SPI master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which SPI mode is supported. P/N: PM1168 shift in SCLK SCLK MSB 9 MX25L1605 shift out MSB REV. 1.3, NOV. 06, 2006 ...

Page 10

... The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of second-byte followings: 15(hex) for MX25L1605. The sequence of issuing RDID instruction is: CS# goes low-> sending RDID instruction code -> 24-bits ID data out on SO -> ...

Page 11

... P/N: PM1168 bit 5 bit 4 bit 3 BP2 BP1 0 the level of the level of the level of protected protected block block (note 1) (note 1) 11 MX25L1605 bit 2 bit 1 BP0 WEL (write enable (write in progress protected latch) block (note 1) 1=write enable 1=write operation 0=not write 0=not in write enable operation REV ...

Page 12

... When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP2, BP1, BP0. The protected area, which is defined by BP2, BP1, BP0 software protected mode (SPM) P/N: PM1168 MX25L1605 WP# and SRWD bit status WP#=1 and SRWD bit=0, or ...

Page 13

... For normal write command (by SI), No effect c. Under parallel mode, the fastest access clock freq. will be changed to 1.5MHz(SCLK pin clock freq.) d. For parallel mode, the tAA will be change to 50ns. P/N: PM1168 TM Memory will be in parallel mode until VCC power-off. 13 MX25L1605 TM REV. 1.3, NOV. 06, 2006 ...

Page 14

... Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed. P/N: PM1168 MX25L1605 14 REV. 1.3, NOV. 06, 2006 ...

Page 15

... RDID instruction. Even in Deep power-down mode, the RDP, RES, and REMS are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. The sequence is shown as Figure 23,24,25. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if P/N: PM1168 MX25L1605 15 REV. 1.3, NOV. 06, 2006 ...

Page 16

... Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Table of ID Definitions: RDID Command manufacturer ID RES Command REMS Command P/N: PM1168 memory type C2 20 manufacturer MX25L1605 memory density 15 electronic ID 14 device ID 14 REV. 1.3, NOV. 06, 2006 ...

Page 17

... At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during the stage while a write, program, erase cycle is in progress. P/N: PM1168 MX25L1605 17 REV. 1.3, NOV. 06, 2006 ...

Page 18

... During voltage transitions, all pins may overshoot to -0.5V to 4.6V 4.6V or -0.5V for period up to 20ns. 4. All input and output pins may overshoot to VCC+0.5V -0.5V to 4.6V while VCC+0.5V is smaller than or equal to 4.6V. Figure 5. Maximum Positive Overshoot Waveform 20ns 4.6V 3.6V MIN. 18 MX25L1605 20ns TYP MAX. UNIT CONDITIONS 10 pF VIN = VOUT = 0V ...

Page 19

... Figure 7. OUTPUT LOADING DEVICE UNDER P/N: PM1168 Input timing referance level 0.7VCC AC Measurement Level 0.3VCC Note: Input pulse rise and fall time are <5ns TEST CL 6.2K ohm CL=30pF Including jig capacitance 19 MX25L1605 Output timing referance level 0.5VCC 2.7K ohm +3.3V DIODES=IN3064 OR EQUIVALENT REV. 1.3, NOV. 06, 2006 ...

Page 20

... VCC+0.4 0.4 VCC-0.2 20 MX25L1605 UNITS TEST CONDITIONS uA VCC = VCC Max VIN = VCC or GND uA VCC = VCC Max VIN = VCC or GND uA VIN = VCC or GND CS# = VCC uA VIN = VCC or GND CS# = VCC mA f=50MHz (serial) mA f=1.5MHz (parallel) mA f=20MHz (serial) mA f=1.2MHz (parallel) ...

Page 21

... Only applicable as a constraint for a WRSR instruction when SRWD is set Test condition is shown as Figure 3. P/N: PM1168 for Commercial grade, VCC = 2.7V ~ 3.6V) Serial Serial Parallel Serial Parallel Serial Parallel Serial Parallel Serial Parallel SRWD, BP2, BP1, BP0 WIP, WEL 21 MX25L1605 Min. Typ. Max. Unit D.C. 50 MHz 1.5 MHz D.C. 20 MHz 1.2 MHz 9 ns 180 ...

Page 22

... Write Inhibit Voltage Note: 1. These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1168 MX25L1605 Min 1.5 22 Max ...

Page 23

... Figure 8. Serial Input Timing CS# tCHSL SCLK tDVCH SI SO Figure 9. Output Timing CS# SCLK tCLQV tCLQX tCLQX SO ADDR.LSB IN SI P/N: PM1168 tSLCH tCHSH tCHDX tCLCH MSB High-Z tCH tCLQV 23 MX25L1605 tSHSL tSHCH tCHCL LSB tCL tSHQZ LSB tQLQH tQHQL REV. 1.3, NOV. 06, 2006 ...

Page 24

... SI is "don't care" during HOLD operation. Figure 11. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 WP# tWHSL CS# SCLK SI SO P/N: PM1168 tHLCH tCHHL tCHHH tHLQZ High-Z 24 MX25L1605 tHHCH tHHQX tSHWL REV. 1.3, NOV. 06, 2006 ...

Page 25

... High SCLK Command SI 04 High Command 9F Manufacturer Identification High MSB 25 MX25L1605 Device Identification MSB REV. 1.3, NOV. 06, 2006 ...

Page 26

... MSB High command 24-Bit Address MSB 26 MX25L1605 Status Register Out MSB Status Register ...

Page 27

... Command 24 BIT ADDRESS High Dummy Byte DATA OUT MSB 27 MX25L1605 DATA OUT MSB MSB 7 REV. 1.3, NOV. 06, 2006 ...

Page 28

... MSB Command MSB 28 MX25L1605 Data Byte MSB Data Byte 256 MSB Bit Address ...

Page 29

... Command Dummy Bytes MSB X 29 MX25L1605 Stand-by Mode Deep Power-down Mode t RES2 Electronic Signature Out MSB Deep Power-down Mode REV. 1.3, NOV. 06, 2006 ...

Page 30

... Dummy Bytes High ADD ( Manufacturer MSB 30 MX25L1605 t RES1 Stand-by Mode Device MSB MSB REV. 1.3, NOV. 06, 2006 ...

Page 31

... Figure 26. Power-up Timing (max (min) Reset State of the Flash V WI P/N: PM1168 Program, Erase and Write Commands are Ignored Chip Selection is Not Allowed tVSL tPUW 31 MX25L1605 Read Command is Device is fully allowed accessible time REV. 1.3, NOV. 06, 2006 ...

Page 32

... Bit6 of the status register is used to state fail status, bit6=1 means program or erase have been failed. Any new write command will clear this bit. P/N: PM1168 CS SCLK Command A5 SI High SCLK Command B5 SI High MX25L1605 REV. 1.3, NOV. 06, 2006 ...

Page 33

... To read array in parallel mode requires a parallel mode command (55H) before the read command. Once in the parallel mode, eLiteFlash 8. In READ mode, RES mode and REMS mode, MXIC IC will enable output an entire cycle in advance compare with other compatible vendor's spec. P/N: PM1168 TM Memory will not exit parallel mode until power-off. 33 MX25L1605 REV. 1.3, NOV. 06, 2006 ...

Page 34

... Under parallel mode, the fastest access clock freq. will be changed to 1.2MHz(SCLK pin clock freq.). 7. To program in parallel mode requires a parallel mode command (55H) before the program command. Once in the parallel mode, eLiteFlash P/N: PM1168 TM Memory will not exit parallel mode until power-off. 34 MX25L1605 REV. 1.3, NOV. 06, 2006 ...

Page 35

... In serial RDID and RDSR mode, output pin SO will be enabled at 8th clock's rising edge. That means, MXIC's drip will enable output half a cycle in advance compare with other compatible vendor's spec. P/N: PM1168 Command 9F Manufacturer Identification High-Z X Byte output Device Identification TM Memory will not exit parallel mode until power-off. 35 MX25L1605 High-Z REV. 1.3, NOV. 06, 2006 ...

Page 36

... P/N: PM1168 Dummy Bytes Memory will not exit parallel mode until power-off. 36 MX25L1605 RES2 Electronic Signature Out Byte Output Deep Power-down Mode REV. 1.3, NOV. 06, 2006 Stand-by Mode ...

Page 37

... In serial RDID and RDSR mode, output pin SO will be enabled at 8th clock's rising edge. That means, MXIC's drip will enable output half a cycle in advance compare with other compatible vendor's spec. P/N: PM1168 TM Memory will not exit parallel mode until power-off. 37 MX25L1605 REV. 1.3, NOV. 06, 2006 ...

Page 38

... Command 2 Dummy Bytes High ADD ( Manufacturer ID X Device ID TM Memory will not exit parallel mode until power-off. 38 MX25L1605 REV. 1.3, NOV. 06, 2006 ...

Page 39

... For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1168 tCHSL tSLCH tDVCH tCHDX MSB IN High Impedance Figure A. AC Timing at Device Power-Up Notes 1 39 MX25L1605 tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN Min. Max. Unit 0.5 500000 us/V ...

Page 40

... Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1168 Min. TYP. (1) Max. (2) UNIT 0.8 2 2.4 9.6 mS 10K cycles 100K cycles 40 MX25L1605 Comments Note (4) Note (4) Note (4) Note (4) Excludes system level overhead(3) MIN. MAX. -1.0V 12.5V -1.0V 2 VCCmax -1.0V VCC + 1.0V -100mA +100mA REV. 1.3, NOV. 06, 2006 ...

Page 41

... ORDERING INFORMATION PART NO. ACCESS TIME(ns) MX25L1605MC-20 MX25L1605MC-20G MX25L1605MI-20 MX25L1605MI-20G P/N: PM1168 OPERATING STANDBY CURRENT(mA) CURRENT(uA MX25L1605 Temperature PACKAGE 50 0~70 C 16-SOP 50 0~70 C 16-SOP 50 -40~85 C 16-SOP 50 -40~85 C 16-SOP REV. 1.3, NOV. 06, 2006 Remark Pb-free Pb-free ...

Page 42

... PART NAME DESCRIPTION MX 25 P/N: PM1168 L 1605 MX25L1605 OPTION: G: Pb-free blank: normal SPEED: 20: 50MHz, for SPI TEMPERATURE RANGE: C: Commercial (0˚C to 70˚C) I: Industrial (-40˚C to 85˚C) PACKAGE: M: 300mil 16-SOP DENSITY & MODE: 1605: 16Mb TYPE DEVICE: 25: Serial Flash ...

Page 43

... PACKAGE INFORMATION P/N: PM1168 MX25L1605 43 REV. 1.3, NOV. 06, 2006 ...

Page 44

... REVISION HISTORY Revision No. Description 1.0 1. Removed "Preliminary" title 2. Added "Recommended Operating Conditions" 3. Added "additional 4Kb erase time" and "cycle time" 4. Removed SON Pb Part Name 5. Added "Part Name Description" separated from MX25L1605, MX25L3205, MX25L6405 to MX25L1605 1.1 1. Removed SON package 1.2 1. Format change 1.3 1. Added statement ...

Page 45

... Macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications. MX25L1605 45 ...

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