MX25L1605 Macronix International, MX25L1605 Datasheet - Page 13

• Manufacturer Part Number: MX25L1605
• Description: 16M-BIT [x 1] CMOS SERIAL FLASH
• Manufacturer: Macronix International

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(6) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling
edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically
increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
READ instruction. The address counter rolls over to 0 when the highest address has been reached.
The sequence of issuing READ instruction is: CS# goes low-> sending READ instruction code-> 3-byte address on SI
-> data out on SO-> to end READ operation can use CS# to high at any time during data out. (see Figure. 17)
(7) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of
each bit shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location.
The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory
can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has
been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low-> sending FAST_READ instruction code-> 3-byte
address on SI-> 1-dummy byte address on SI->data out on SO-> to end FAST_READ operation can use CS# to high at
any time during data out. (see Figure. 18)
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(8) Parallel Mode (Highly recommended for production throughputs increasing)
The parallel mode provides 8 bit inputs/outputs for increasing throughputs of factory production purpose. The parallel mode
requires 55H command code, after writing the parallel mode command and then CS# going high, after that, the eLiteFlash
Memory can be available to accept read/program/read status/read ID/RES/REMS command as the normal writing
command procedure. The eLiteFlash
a. Only effective for Read Array for normal read(not FAST_READ), Read Status, Read ID, Page Program, RES and REMS
b. For normal write command (by SI), No effect
c. Under parallel mode, the fastest access clock freq. will be changed to 1.5MHz(SCLK pin clock freq.)
d. For parallel mode, the tAA will be change to 50ns.
Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously been
set. It is rejected to write the Status Register and not be executed.
Hardware Protected Mode (HPM):
-
Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered. If the
WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software
protected mode via BP2, BP1, BP0.
P/N: PM1168
write data period. (refer to Figure 29~34)
When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected mode
(HPM). The data of the protected area is protected by software protected mode by BP2, BP1, BP0 and hardware
protected mode by the WP# to against data modification.
TM
Memory will be in parallel mode until VCC power-off.
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MX25L1605
REV. 1.3, NOV. 06, 2006
TM