MT312 Zarlink Semiconductor, MT312 Datasheet - Page 56

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

10.0
10.1
There are four MOCLK modes of operation, controlled by register bits.
10.1.1
In this mode MOCLK is generated from the symbol clock. MOCLK will be a continuously running clock once symbol
lock has been achieved in the QPSK block.
10.1.2
In this mode MOCLK is not generated from the symbol clock but instead uses the data in the QPSK decimation
ratio. This mode is not normally used but is available for engineering test purposes.
10.1.3
This is the Programmable Clock Division Ratio mode of operation. MOCLK is generated by dividing the PLL clock
frequency by the MOCLK_RATIO + 6 see register 33 on see “FEC_STATUS output enable register 33 (R/W)” on
page 50.
The range of values of 6 to 9 for (MOCLK_RATIO + 6) will guarantee operation for 2 - 45 MSym/s. However, for a
restricted range of symbol rates, higher (MOCLK_RATIO + 6) values may be used with a lower MOCLK frequency.
The equation in “Data output timing” on page 61 must be evaluated to ensure successful operation and avoid buffer
overflow in the MT312.
MOCLK frequency =
MANUAL MOCLK
(register 96 bit 7)
PLL Frequency
MPEG clock modes
MPEG Packet Data Output
MANUAL MOCLK = 0 and DIS_SR = 0.
MANUAL MOCLK = 0 and DIS_SR = 1.
MANUAL MOCLK = 1 and DIS_SR = 0
60MHz
60MHz
90MHz
91MHz
0
0
1
1
Table 8 - MOCLK Input Minimum And Maximum Frequencies
(MCLK_RATIO + 6)
PLL frequency
(register 97 bit 7)
DIS_SR
0
1
0
1
Moclk Ratio + 6
Table 7 - MPEG Clock Modes
6
9
6
9
Zarlink Semiconductor Inc.
Manually set MOCLK period from MOCLK_RATIO (reg. 33).
MT312
Disable use of symbol rate for MOCLK generation.
Use external MICLK (pin 14) signal for MOCLK.
56
Use symbol rate for MOCLK generation.
MOCLK generation mode
Moclk Frequency
10.111MHz
6.667MHz
10.0MHz
15MHz
Design Manual
Comment
maximum
maximum
minimum
minimum