MT312 Zarlink Semiconductor, MT312 Datasheet - Page 42

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

7.1.3
bit-7:
bit-6:
bit-5:
bit-4:
bit-3:
bit-2:
bit-1:
bit-0:
If either of the two DSS control bits of the Configuration Register (127) is active (section 4.2), then bit-0 (ROLL_20)
is ignored and the matched filter root-raised-cosine roll-off factor is taken as 0.20. Hence this bit only allows the
choice of roll-off in the DVB mode.
If the Q_IQ_SP bit is not set correctly, i.e. according to the hardware in use, the AUT_IQ bit in the VIT_MODE
register [see Viterbi mode register 25 (R/W)] will allow the system to lock, but calculated frequency offsets will have
the wrong sign, and may confuse the software.
7.1.4
bit-7-1:
bit-0:
If this register is read, it will return zero.
QPSK_CTRL
NAME
GO
NAME
QPSK control register 26 (R/W)
Go command register 27 (R/W)
ADR
Q_IQ_SP
AFC_M
Reserved - not used.
GO
Rsvd
Reserved
Reserved
ROLL_20
27
Reserved
Reserved
ADR
26
bit-7
Rsvd
bit-7
bit-6
Q_IQ_SP
Must be set low.
Swap I and Q inputs before QPSK demodulation to overcome spectral inversion
caused by the receiver front-end, for example through the swapping I and Q wires
on the board.
High = I-Q swap
Low = No I-Q swap
Must be set low.
Must be set low.
Must be set low.
High = Use AFC mode, for low symbol rates only, < 10MSym/s.
Must be set low.
High = Roll-off 0.20
Low = Roll-off 0.35
High = release reset state to start signal capture, automatically reset to zero.
Low = no action.
bit-6
bit-5
Reserved
bit-4
Rsvd
bit-5
Zarlink Semiconductor Inc.
bit-3
Rsvd
bit-4
MT312
42
bit-2
Rsvd
bit-3
bit-1
AFC_M
bit-2
bit-0
GO
Rsvd
bit-1
R/W
ROLL_20
bit-0
hex
Def
00
R/W
Design Manual
hex
Def
00