SC18IS603 NXP Semiconductors, SC18IS603 Datasheet
SC18IS603
Related parts for SC18IS603
SC18IS603 Summary of contents
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... I C-bus to SPI bridge Rev. 04 — 11 March 2008 1. General description The SC18IS602/602B and SC18IS603 are designed to serve as an interface between a standard I communicate directly with SPI devices through its I operates SC18IS602/602B/603 controls all the SPI bus-specific sequences, protocol, and timing. ...
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... Unused slave select outputs may be used for GPIO. Fig 1. Block diagram of SC18IS602/602B SCL SDA RESET INT (1) Unused slave select outputs may be used for GPIO; SC18IS603 does not have SS3. Fig 2. Block diagram of SC18IS603 SC18IS602_602B_603_4 Product data sheet Description plastic thin shrink small outline package; 16 leads; body width 4.4 mm plastic thin shrink small outline package ...
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... SS3/GPIO3 13 - CLKIN - [1] SC18IS602IPW and SC18IS603IPW do not support SS2. This pin should be used as GPIO2 only. [2] SC18IS602BIPW does support SS2/GPIO2 function. This pin can be used as SS2 or GPIO2. SC18IS602_602B_603_4 Product data sheet 16 A2 SS0/GPIO0 15 A1 SS1/GPIO1 14 A0 RESET 13 SS3/GPIO3 ...
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... SC18IS602/602B/603 2 C-bus configuration 2 C-bus master is reading data from SC18IS60x, Rev. 04 — 11 March 2008 SC18IS602/602B/603 2 I C-bus to SPI bridge www.DataSheet4U.com 2 C-bus and an SPI interface. It Figure 4. (Refer to NXP Semiconductors’ SDA SCL C-BUS I C-BUS DEVICE DEVICE 002aac445 2 C-bus interface that supports ...
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... NXP Semiconductors 7.1.1 Addressing Fig 5. Slave address The first seven bits of the first byte sent after a START condition defines the slave address of the device being accessed on the bus. The eighth bit determines the direction of the message. A ‘0’ in the least significant position of the first byte means that the master will write information to a selected slave. A ‘ ...
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... SS3 does not exist in the SC18IS603. [2] SS2 does not exist in the SC18IS602 and SC18IS603. Only SC18IS602B supports this function. The data on the SPI port will contain the same information as the I the slave address and Function ID. For example, if the message shown in transmitted on the I ...
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... SPICLK HIGH when idle; data clocked in on trailing edge (CPOL = 1, CPHA = SPICLK HIGH when idle; data clocked in on leading edge (CPOL = 1, CPHA = 1) F1:F0 SPI clock rate SC18IS602/602B 1843 kHz 01 - 461 kHz 10 - 115 kHz kHz SC18IS603: fosc fosc fosc fosc ...
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... SS0, if they are configured as GPIO. The Port Enable function will define if these pins are used as SPI Slave Selects or if they are GPIO. Table 6. Bit Symbol Reset [1] SS3 does not exist in the SC18IS603. SC18IS602_602B_603_4 Product data sheet S SLAVE ADDRESS S SLAVE ADDRESS 2 C-bus address is detected ...
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... The data byte following the F6h command byte will determine which pins can be used as GPIO. A logic 1 will enable the pin as a GPIO, while a logic 0 will disable GPIO control. Table [1] SS3 does not exist in the SC18IS603. SC18IS602_602B_603_4 Product data sheet S SLAVE ADDRESS W ...
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... Two configuration bits in GPIO Configuration register for each pin select the type for each pin. A pin has Schmitt-triggered input that also has a glitch suppression circuit. For SC18IS603, the SS3 pin defined as GPIO is non-existent. 7.1.11.1 Quasi-bidirectional output configuration Quasi-bidirectional outputs can be used both as an input and output without the need to reconfi ...
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... NXP Semiconductors A second pull-up, called the ‘weak’ pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting this pin is pulled LOW by an external device, the weak pull-up turns off, and only the very weak pull-up remains on ...
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... NXP Semiconductors Fig 17. Open-drain output configuration 7.1.11.3 Input-only configuration The input-only pin configuration is shown in also has a glitch suppression circuit. Fig 18. Input-only configuration 7.1.11.4 Push-pull output configuration The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes but provides a continuous strong pull-up when the port latch contains a logic 1 ...
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... SPI interface The SPI interface can support Mode 0 through Mode 3 of the SPI specification and can operate up to 1.8 Mbit/s (SC18IS602/602B) or 4.0 Mbit/s (SC18IS603). The SPI interface uses at least four pins: SPICLK, MOSI, MISO, and Slave Select (SSn). SSn are the slave select pins typical configuration, an SPI master selects one SPI device as the current slave ...
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... NXP Semiconductors C-bus to SPI communications example The following example describes a typical sequence of events required to read the contents of an SPI-based EEPROM. This example assumes that the SC18IS602/602B/603 is configured to respond to address 50h. A START condition is shown as ‘ST’, while a STOP condition is ‘SP’. The data is presented in hexadecimal format. 1. The fi ...
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... NXP Semiconductors You can see that on the I SPI bus. The first byte is the SC18IS60x address, followed by three dummy data bytes. These dummy data bytes correspond to the three bytes sent to the EEPROM before it actually places data on the bus (command 03h, subaddress 0030h). ...
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... NXP Semiconductors 10. Static characteristics Table 12. Static characteristics +85 C (industrial); unless otherwise specified. DD amb Symbol Parameter I operating supply current DD(oper) I Idle mode supply current DD(idle) V HIGH-LOW threshold voltage th(HL) V LOW-HIGH threshold voltage th(LH) V hysteresis voltage hys V LOW-level output voltage ...
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... NXP Semiconductors 11. Dynamic characteristics Table 13. Dynamic characteristics +85 C (industrial); unless otherwise specified. DD amb Symbol Parameter f internal RC oscillator osc(RC) frequency External clock input f oscillator frequency osc T clock cycle time CLCL t clock HIGH time CHCX t clock LOW time ...
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... NXP Semiconductors SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t SPIF MOSI (output) Fig 20. SPI master timing (CPHA = 0) SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t SPIF MOSI (output) Fig 21. SPI master timing (CPHA = 0.45 V Fig 22. External clock timing SC18IS602_602B_603_4 ...
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... NXP Semiconductors 12. Package outline TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors temperature MSL: Moisture Sensitivity Level Fig 24. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Abbreviations Table 16. Acronym CDM CPU EEPROM ESD GPIO HBM ...
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... NXP Semiconductors 15. Revision history Table 17. Revision history Document ID Release date SC18IS602_602B_603_4 20080311 • Modifications: added Type number SC18IS602BIPW • Section 1 “General • Section 6 “Pinning – added “SC18IS602BIPW” to – Table 2 “Pin pin 10 • Table 3 “Function ID 01h to • Section 7.1 “I SC18IS602_603_3 ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... GPIO Enable - Function ID F6h . . . . . . . . . . . . 9 7.1.11 GPIO Configuration - Function ID F7h . . . . . . 10 7.1.11.1 Quasi-bidirectional output configuration . . . . . 10 7.1.11.2 Open-drain output configuration . . . . . . . . . . . 11 7.1.11.3 Input-only configuration . . . . . . . . . . . . . . . . . 12 7.1.11.4 Push-pull output configuration . . . . . . . . . . . . 12 7.2 External clock input (SC18IS603 7.3 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . C-bus to SPI communications example . . . 14 9 Limiting values Static characteristics Dynamic characteristics ...