SC16C850V NXP Semiconductors, SC16C850V Datasheet - Page 24

• Manufacturer Part Number: SC16C850V
• Description: XScale VLIO bus interface
• Manufacturer: NXP Semiconductors

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NXP Semiconductors
SC16C850V_4
Product data sheet
7.5 Line Control Register (LCR)
Table 13.
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.
Table 14.
Table 15.
Table 16.
Bit
0
Bit
7
6
5:3
2
1:0
LCR[5]
X
X
0
0
1
LCR[2]
0
1
1
Symbol
LCR[7]
LCR[6]
LCR[5:3]
LCR[2]
LCR[1:0]
Symbol
ISR[0]
LCR[4]
X
0
1
0
1
Interrupt Status Register bits description
Line Control Register bits description
LCR[5:3] parity selection
LCR[2] stop bit length
Word length (bits)
5, 6, 7, 8
5
6, 7, 8
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Description
Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
Set break. When enabled, the Break control bit causes a break condition to be
transmitted (the TX output is forced to a logic 0 state). This condition exists
until disabled by setting LCR[6] to a logic 0.
Programs the parity conditions (see
Stop bits. The length of stop bit is specified by this bit in conjunction with the
programmed word length (see
Word length bits 1, 0. These two bits specify the word length to be transmitted
or received (see
LCR[3]
0
1
1
1
1
Description
INT status.
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
logic 0 or cleared = default condition
logic 0 or cleared = default condition
Rev. 04 — 14 January 2008
logic 0 = an interrupt is pending and the ISR contents may be used as a
pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
Parity selection
no parity
odd parity
even parity
forced parity ‘1’
forced parity ‘0’
Stop bit length (bit times)
1
1
2
1
Table
2
17).
Table
…continued
Table
16).
15).
SC16C850V
© NXP B.V. 2008. All rights reserved.
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