SC16C850V NXP Semiconductors, SC16C850V Datasheet - Page 12
SC16C850V
Manufacturer Part Number
SC16C850V
Description
XScale VLIO bus interface
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C850V.pdf
(47 pages)
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NXP Semiconductors
SC16C850V_4
Product data sheet
Table 6.
Output
baud rate
(bit/s)
50
75
110
150
300
600
1.2 k
2.4 k
3.6 k
4.8 k
7.2 k
9.6 k
19.2 k
38.4 k
57.6 k
115.2 k
Fig 4.
Fig 5.
Crystal oscillator connection
If f
XTAL2 pin should be left unconnected when an external clock is used.
External clock connection
Baud rate generator programming table using a 1.8432 MHz clock with MCR[7] = 0
and CLKPRE[3:0] = 0
XTAL1
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Output
16 clock divisor
(decimal)
2304
1536
1047
768
384
192
96
48
32
24
16
12
6
3
2
1
frequency is greater than 50 MHz, then a DC blocking capacitor is required.
Rev. 04 — 14 January 2008
XTAL1
1.8432 MHz
C1
22 pF
X1
f
XTAL1
XTAL2
Output
16 clock divisor
(hexadecimal)
900
600
417
300
180
C0
60
30
20
18
10
0C
06
03
02
01
C2
33 pF
100 pF
XTAL1
XTAL1
XTAL2
002aac630
1.8432 MHz
C1
22 pF
DLM
program value
(hexadecimal)
09
06
04
03
01
00
00
00
00
00
00
00
00
00
00
00
X1
XTAL2
002aaa870
1.5 k
C2
47 pF
SC16C850V
© NXP B.V. 2008. All rights reserved.
DLL
program value
(hexadecimal)
00
00
17
00
80
C0
60
30
20
18
10
0C
06
03
02
01
12 of 47
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