LTC3589 Linear Technology, LTC3589 Datasheet - Page 33

• Manufacturer Part Number: LTC3589
• Description: 8-Output Regulator
• Manufacturer: Linear Technology

OPERATION
I
The I
built-in timing delays to ensure correct operation when
addressed from an I
contains input fi lters designed to suppress glitches should
the bus become corrupted.
I
A bus master signals the beginning of communications
by transmitting a START condition. A START condition is
generated by transitioning SDA from HIGH to LOW while
SCL is HIGH. The master may transmit either the slave
write or the slave read address. Once data is written to the
LTC3589, the master may transmit a STOP condition that
commands the LTC3589 to act upon its new command set.
A STOP condition is sent by the master by transitioning
SDA from LOW to HIGH while SCL is HIGH. The bus it then
free for communication with another I
SDA
SCL
2
2
C Bus Speed
C START and STOP Conditions
START
2
C port operates at speeds up to 400kHz. It has
1
0
0
SDA
SCL
t
1
1
2
HD, STA
1
3
1
ADDRESS
CONDITION
0
4
0
START
1
5
1
0
6
0
2
0 WR
0
7
C compliant master device. It also
t
LOW
0
8
ACK
9
t
S7 S6 S5 S4 S3 S2 S1 S0
r
1
t
HIGH
2
t
SU, DAT
SUB-ADDRESS
3
Figure 19. LTC3589 I
t
4
f
2
5
C device.
6
7
t
HD, DAT
Figure 18. LTC3589 I
8
ACK
9
D7 D6 D5 D4 D3 D2 D1 D0
1
2
2
C Serial Port Multiple Write Pattern
3
REPEATED START
4
DATA
CONDITION
5
I
Each byte sent to or received from the LTC3589 must
be 8 bits long followed by an extra clock cycle for the
acknowledge bit. The data should be sent to the LTC3589
most signifi cant bit (MSB) fi rst.
I
The acknowledge signal is used for handshaking between
the master and the slave. When the LTC3589 is written
to (write address), it acknowledges its write address and
subsequent register address and data bytes. When read-
ing from the LTC3589, it acknowledges its read address
and 8-bit status byte.
An acknowledge pulse (active LOW) generated by the
LTC3589 lets the master know that the latest byte of informa-
tion was transferred. The master generates the clock cycle
and releases the SDA line (HIGH) during the acknowledge
2
2
6
C Byte Format
C Acknowledge
2
C Timing
7
t
HD, STA
8
ACK
9
t
HD, STA
S7 S6 S5 S4 S3 S2 S1 S0
1
t
SP
2
3
SUB-ADDRESS
4
5
6
7
8
ACK
9
STOP
D7 D6 D5 D4 D3 D2 D1 D0
1
t
2
SU, STO
t
BUF
3
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4
DATA
LTC3589
START
5
3589 F18
6
7
8
33
ACK
9
3589p
3589 F19
STOP