LTC2355-14 Linear Technology, LTC2355-14 Datasheet - Page 7

• Manufacturer Part Number: LTC2355-14
• Description: (LTC2355-12/-14) 3.5Msps Sampling ADCs
• Manufacturer: Linear Technology

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BLOCK DIAGRA
PI FU CTIO S
A
fully differentially with respect to A
differential swing and a 0V to V
A
differentially with respect to A
differential swing and a 0V to V
V
to a solid analog ground plane with a 10µF ceramic
capacitor (or 10µF tantalum in parallel with 0.1µF ce-
ramic). Can be overdriven by an external reference be-
tween 2.55V and V
GND (Pins 4, 5, 6, 11): Ground and Exposed Pad. These
ground pins and the exposed pad must be tied directly to
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
flow through these pins.
V
supplies 3.3V to the entire device. Bypass to GND and to
a solid analog ground plane with a 10µF ceramic capacitor
IN
IN
REF
DD
U
+
–
(Pin 7): 3.3V Positive Supply. This single power pin
(Pin 2): Inverting Analog Input. A
(Pin 1): Noninverting Analog Input. A
(Pin 3): 2.5V Internal Reference. Bypass to GND and
U
10µF
DD
U
A
A
.
IN
IN
+
–
W
1
2
3
4
LTC2355-14
V
GND
DD
DD
REF
IN
5
+
–
+
S & H
common mode swing.
common mode swing.
IN
with a – 2.5V to 0V
6
–
REFERENCE
with a 0V to 2.5V
IN
–
2.5V
operates fully
IN
+
14-BIT ADC
11
operates
10µF
EXPOSED PAD
3.3V
7
V
DD
(or 10µF tantalum in parallel with 0.1µF ceramic). Keep in
mind that internal analog currents and digital output signal
currents flow through this pin. Care should be taken to
place the 0.1µF bypass capacitor as close to Pins 6 and 7
as possible.
SDO (Pin 8): Three-State Serial Data Output. Each set of
output data words represents the difference between
A
conversion.
SCK (Pin 9): External Clock Input. Advances the conver-
sion process and sequences the output data on the rising
edge. Responds to TTL (≤3.3V) and 3.3V CMOS levels.
One or more SCK pulses wakes the ADC from sleep mode.
CONV (Pin 10): Convert Start. Holds the analog input
signal and starts the conversion on the rising edge.
Responds to TTL (≤3.3V) and 3.3V CMOS levels. Two
CONV pulses with SCK in fixed high or fixed low state start
Nap mode. Four or more CONV pulses with SCK in fixed
high or fixed low state start Sleep mode.
IN
14
+
and A
IN
LTC2355-12/LTC2355-14
OUTPUT
THREE-
TIMING
SERIAL
–
STATE
LOGIC
PORT
analog inputs at the start of the previous
10
8
9
2355 BD
SDO
CONV
SCK
7
2355f