LTC1403 Linear Technology, LTC1403 Datasheet - Page 7

• Manufacturer Part Number: LTC1403
• Description: Serial 12-Bit/14-Bit/ 2.8Msps Sampling ADCs with Shutdown
• Manufacturer: Linear Technology

BLOCK DIAGRA
PI FU CTIO S
A
fully differentially with respect to A
differential swing and a 0V to V
A
differentially with respect to A
differential swing and a 0V to V
V
to a solid analog ground plane with a 10 F ceramic
capacitor (or 10 F tantalum in parallel with 0.1 F ce-
ramic). Can be overdriven by an external reference be-
tween 2.55V and V
GND (Pins 5, 6, 11): Ground and Exposed Pad. These
ground pins and the exposed pad must be tied directly to
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
flow through these pins.
V
supplies 3V to the entire chip. Bypass to GND and to a solid
analog ground plane with a 10 F ceramic capacitor (or
IN
IN
REF
DD
U
+
–
(Pin 7): 3V Positive Supply. This single power pin
(Pin 2): Inverting Analog Input. A
(Pin 1): Noninverting Analog Input. A
(Pin 3): 2.5V Internal Reference. Bypass to GND and
U
DD
U
.
10 F
A
A
IN
IN
W
+
–
DD
DD
IN
1
2
3
4
LTC1403A
+
common mode swing.
common mode swing.
V
GND
REF
IN
with a – 2.5V to 0V
5
+
–
–
S & H
with a 0V to 2.5V
IN
6
–
operates fully
REFERENCE
IN
2.5V
+
operates
14-BIT ADC
11
10 F
EXPOSED PAD
3V
7
10 F tantalum in parallel with 0.1 F ceramic). Keep in
mind that internal analog currents and digital output signal
currents flow through this pin. Care should be taken to
place the 0.1 F bypass capacitor as close to Pins 6 and 7
as possible.
SDO (Pin 8): Three-State Serial Data Output. Each of
output data words represents the difference between
A
conversion.
SCK (Pin 9): External Clock Input. Advances the conver-
sion process and sequences the output data on the rising
edge. Responds to TTL ( 3V) and 3V CMOS levels. One
or more pulses wake from sleep.
CONV (Pin 10): Convert Start. Holds the analog input
signal and starts the conversion on the rising edge.
Responds to TTL ( 3V) and 3V CMOS levels. Two pulses
with SCK in fixed high or fixed low state start Nap mode.
Four or more pulses with SCK in fixed high or fixed low
state start Sleep mode.
V
IN
DD
+
and A
14
IN
–
analog inputs at the start of the previous
OUTPUT
THREE-
TIMING
SERIAL
LOGIC
STATE
PORT
LTC1403/LTC1403A
10
8
9
1403A BD
SDO
CONV
SCK
1403af
7