LTC1403 Linear Technology, LTC1403 Datasheet - Page 4

• Manufacturer Part Number: LTC1403
• Description: Serial 12-Bit/14-Bit/ 2.8Msps Sampling ADCs with Shutdown
• Manufacturer: Linear Technology

POWER REQUIRE E TS
LTC1403/LTC1403A
range, otherwise specifications are at T
SYMBOL
V
I
P
range, otherwise specifications are at T
SYMBOL
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: When these pins are taken below GND or above V
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V
Note 4: Offset and full-scale specifications are measured for a single-
ended A
Note 5: Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defined for the voltage difference
between A
Note 9: The absolute voltage at A
Note 10: If less than 3ns is allowed, the output data will appear one clock
4
TI I G CHARACTERISTICS
DD
SAMPLE(MAX)
THROUGHPUT
SCK
CONV
1
2
3
4
5
6
7
8
9
10
12
DD
D
W U
IN
+
IN
input with A
+
and A
PARAMETER
Supply Voltage
Positive Supply Voltage
Power Dissipation
PARAMETER
Maximum Sampling Frequency per Channel
(Conversion Rate)
Minimum Sampling Period (Conversion + Acquisiton Period)
Clock Period
Conversion Time
Minimum Positive or Negative SCLK Pulse Width
CONV to SCK Setup Time
Nearest SCK Edge Before CONV
Minimum Positive or Negative CONV Pulse Width
SCK to Sample Mode
CONV to Hold Mode
16th SCK to CONV Interval (Affects Acquisition Period)
Minimum Delay from SCK to Valid Bits 0 Through 13
SCK to Hi-Z at SDO
Previous SDO Bit Remains Valid After SCK
V
REF
IN
–
Settling Time After Sleep-to-Wake Transition
.
IN
–
grounded and using the internal 2.5V reference.
IN
+
and A
W U
DD
IN
–
without latchup.
A
A
must be within this range.
= 25 C. (Note 17)
= 25 C. V
CONDITIONS
Active Mode
Nap Mode
Sleep Mode (LTC1403)
Sleep Mode (LTC1403A)
Active Mode with SCK in Fixed State (Hi or Lo)
The
DD
DD
, they will be
The
= 3V
denotes the specifications which apply over the full operating temperature
denotes the specifications which apply over the full operating temperature
CONDITIONS
(Note 16)
(Note 6)
(Note 6)
(Notes 6, 10)
(Note 6)
(Note 6)
(Note 6)
(Notes 6, 11)
(Notes 6, 7, 13)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 14)
cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns)
because the 2.2ns delay through the sample-and-hold is subtracted from
the CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
16th rising clock and it is ended by the rising edge of convert.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10 F capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops to 3dB with a 2.5V
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read without an arbitrarily long clock.
Note 17: V
Note 18: The LTC1403A is measured and specified with 14-bit Resolution
(1LSB = 152 V) and the LTC1403 is measured and specified with 12-bit
Resolution (1LSB = 610 V).
DD
= 3V, f
SAMPLE
= 2.8Msps.
P-P
19.8
MIN
MIN
2.7
2.8
1.2
16
45
2
3
0
4
4
8
6
2
input sine wave.
TYP
TYP
4.7
1.1
12
18
2
2
2
10000
MAX
MAX
357
3.6
1.5
15
10
7
SCLK cycles
UNITS
UNITS
1403af
MHz
mW
mA
mA
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
A
A