LTC1096 Linear Technology, LTC1096 Datasheet - Page 19

• Manufacturer Part Number: LTC1096
• Description: Micropower Sampling 8-Bit Serial I/O A/D Converters
• Manufacturer: Linear Technology

A
in and continues until the falling CLK edge after the MSBF
bit is received. On this falling edge, the S&H goes into hold
mode and the conversion begins.
Differential Inputs
With differential inputs, the ADC no longer converts just a
single voltage but rather the difference between two volt-
ages. In this case, the voltage on the selected “+” input is
still sampled and held and therefore may be rapidly time
varying just as in single-ended mode. However, the volt-
age on the selected “–” input must remain constant and be
free of noise and ripple throughout the conversion time.
Otherwise, the differencing operation may not be per-
formed accurately. The conversion time is 8 CLK cycles.
Therefore, a change in the “–” input voltage during this
interval can cause conversion errors. For a sinusoidal
voltage on the “–” input this error would be:
Where f(“–”) is the frequency of the “–” input voltage,
V
CLK. In most cases V
60Hz signal on the “–” input to generate a 1/4LSB error
(5mV) with the converter running at CLK = 500kHz, its
peak value would have to be 750mV.
ANALOG INPUTS
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1096(L)/
LTC1098(L )have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem. However, if large source resistances are used or
if slow settling op amps drive the inputs, care must be
taken to ensure that the transients caused by the current
spikes settle completely before the conversion begins.
“+” Input Settling
The input capacitor of the LTC1096(L) is switched onto
“+” input during the wake-up time (see Figure 1) and
samples the input signal within that time. However, the
input capacitor of the LTC1098(L) is switched onto “+”
input during the sample phase (t
sample phase is 1.5 CLK cycles before conversion starts.
The voltage on the “+” input must settle completely within
PEAK
PPLICATI
V
ERROR (MAX)
is its peak amplitude and f
= V
O
U
PEAK
ERROR
S
• 2 • • f(“–”) • 8/f
I FOR ATIO
U
will not be significant. For a
CLK
SMPL
is the frequency of the
W
, see Figure 7). The
CLK
U
t
respectively. Minimizing R
the input settling time. If a large “+” input source resis-
tance must be used, the sample time can be increased by
using a slower CLK frequency.
“–” Input Settling
At the end of the t
switches to the “–” input and conversion starts (see
Figures 1 and 7). During the conversion the “+” input
voltage is effectively “held” by the sample-and-hold and
will not affect the conversion result. However, it is critical
that the “–” input voltage settles completely during the
first CLK cycle of the conversion time and be free of noise.
Minimizing R
a large “–” input source resistance must be used, the time
allowed for settling can be extended by using a slower CLK
frequency.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 7). Again, the “+” and “–” input sampling times
can be extended as described above to accommodate
slower op amps. Most op amps, including the LT1006 and
LT1413 single supply op amps, can be made to settle well
even with the minimum settling windows of 3 s (“+”
input) which occur at the maximum clock rate of 500kHz.
Source Resistance
The analog inputs of the LTC1096/LTC1098 look like a
25pF capacitor (C
as shown in Figure 8. C
selected “+” and “–” inputs once during each conversion
WAKEUP
V
V
IN
IN
+
–
or t
R
R
SOURCE
SOURCE
Figure 8. Analog Input Equivalent Circuit
SMPL
SOURCE
+
–
IN
for the LTC1096(L) or the LTC1098(L)
WAKEUP
) in series with a 500 resistor (R
–
C1
INPUT
INPUT
C2
and C2 will improve settling time. If
“+”
“–”
LTC1096/LTC1096L
LTC1098/LTC1098L
IN
SOURCE
or t
gets switched between the
SMPL
R
+
ON
, the input capacitor
and C1 will improve
= 500
C
LTC1096
LTC1098
IN
LTC1096/8 • F8
= 25pF
19
ON
)