LT1711 Linear Technology, LT1711 Datasheet - Page 8

• Manufacturer Part Number: LT1711
• Description: 4ns/ 150MHz Dual Comparator with Independent Input/Output Supplies
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LT1715
responds correctly to a small differential input signal. If
one input is within the common mode limit, the other input
signal can go outside the common mode limits, up to the
absolute maximum limits, and the output will retain the
correct polarity.
When either input signal falls below the negative common
mode limit, the internal PN diode formed with the sub-
strate can turn on, resulting in significant current flow
through the die. An external Schottky clamp diode
between the input and the negative rail can speed up
recovery from negative overdrive by preventing the sub-
strate diode from turning on.
When both input signals are below the negative common
mode limit, phase reversal protection circuitry prevents
false output inversion to at least – 400mV common mode.
However, the offset and hysteresis in this mode will
increase dramatically, to as much as 15mV each. The input
bias currents will also increase.
When one input signal goes above the common mode
range without exceeding a diode drop above the input
supply rail, the input stage will remain biased and the
comparator will maintain correct output polarity. Above
this voltage, the input stage current source will saturate
completely and the ESD protection diode will forward
conduct. Once the aberrant input falls back into the com-
mon mode range, the comparator will respond correctly to
valid input signals within less than 10ns.
When both input signals are above the positive common
mode limit, the input stage will get debiased and the output
polarity will be random. However, the internal hysteresis
will hold the output to a valid logic level. When at least one
of the inputs returns to within the common mode limits,
recovery from this state will take as long as 1 s.
The propagation delay does not increase significantly
when driven with large differential voltages, but with low
levels of overdrive, an apparent increase may be seen with
large source resistances due to an RC delay caused by the
2pF typical input capacitance.
Input Protection
The input stage is protected against damage from large
differential signals, up to and beyond a differential voltage
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equal to the supply voltage, limited only by the absolute
maximum currents noted. External input protection cir-
cuitry is only needed if currents would otherwise exceed
these absolute maximums. The internal catch diodes can
conduct current up to these rated maximums without
latchup, even when the supply voltages are at the absolute
maximum ratings.
The LT1715 input stage has general purpose internal ESD
protection for the human body model. For use as a line
receiver, additional external protection may be required.
As with most integrated circuits, the level of immunity to
ESD is much greater when residing on a printed circuit
board where the power supply decoupling capacitance will
limit the voltage rise caused by an ESD pulse.
Input Bias Current
Input bias current is measured with both inputs held at 1V.
As with any PNP differential input stage, the LT1715 bias
current flows out of the device. It will go to zero on the
higher of the two inputs and double on the lower of the two
inputs. With more than two diode drops of differential
input voltage, the LT1715’s input protection circuitry
activates, and current out of the lower input will increase
an additional 30% and there will be a small bias current
into the higher of the two input pins, of 4 A or less. See the
Typical Performance curve “Input Current vs Differential
Input Voltage.”
High Speed Design Considerations
Application of high speed comparators is often plagued by
oscillations. The LT1715 has 4mV of internal hysteresis,
which will prevent oscillations as long as parasitic output
to input feedback is kept below 4mV. However, with the
2V/ns slew rate of the LT1715 outputs, a 4mV step can be
created at a 100 input source with only 0.02pF of output
to input coupling. The LT1715’s pinout has been arranged
to minimize problems by placing the sensitive inputs away
from the outputs, shielded by the power rails. The input
and output traces of the circuit board should also be
separated, and the requisite level of isolation is readily
achieved if a topside ground plane runs between the
output and the inputs. For multilayer boards where the
ground plane is internal, a topside ground or supply trace
should be run between the inputs and the output.