LT1711 Linear Technology, LT1711 Datasheet - Page 11

• Manufacturer Part Number: LT1711
• Description: 4ns/ 150MHz Dual Comparator with Independent Input/Output Supplies
• Manufacturer: Linear Technology

APPLICATIONS
With this in mind, calculation of the resistor values needed
is a two-step process. First, calculate the value of R3 based
on the additional hysteresis desired, the output voltage
swing and the impedance of the primary bias string:
Additional hysteresis is the desired overall hysteresis less
the internal 4mV hysteresis.
The second step is to recalculate R2 to set the same
average threshold as before. The average threshold before
was set at V
calculated based on the average output voltage (+V
and the simplified circuit model in Figure 7. To assure that
the comparator’s noninverting input is, on average, the
same V
For additional hysteresis of 10mV or less, it is not uncom-
mon for R2 to be the same as R2 within 1% resistor
tolerances.
This method will work for additional hysteresis of up to a
few hundred millivolts. Beyond that, the impedance of R3
is low enough to effect the bias string, and adjustment of
R3 = (R1 R2)(+V
R2 = (V
Figure 7. Model for Additional Hysteresis Calculations
TH
as before:
REF
Figure 6. Additional External Hysteresis
V
TH
REF
R2
R1
– V
V
= (V
REF
R2
R1
TH
V
TH
U
INPUT
REF
)/(V
S
+
–
– 0.6V)/(additional hysteresis)
1/2 LT1715
)(R1)/(R1 + R2). The new R2 is
TH
INFORMATION
+
–
1/2 LT1715
U
/R1 + (V
R3
R3
V
TH
W
AVERAGE
1715 F06
– V
1715 F07
=
S
/2)/R3)
+V
2
S
U
S
/2)
R1 may also be required. Note that the currents through the
R1/R2 bias string should be many times the input currents
of the LT1715. For 5% accuracy, the current must be at least
20 times the input current, more for higher accuracy.
Interfacing the LT1715 to ECL
The LT1715’s comparators can be used in high speed
applications where Emitter-Coupled Logic (ECL) is de-
ployed. To interface the output of the LT1715 to ECL logic
inputs, standard TTL/CMOS to ECL level translators such
as the 10H124, 10H424 and 100124 can be used. These
components come at a cost of a few nanoseconds addi-
tional delay as well as supply currents of 50mA or more,
and are only available in quads. A faster, simpler and lower
power translator can be constructed with resistors as
shown in Figure 8.
Figure 8a shows the standard TTL to Positive ECL (PECL)
resistive level translator. This translator cannot be used for
the LT1715, or with CMOS logic, because it depends on the
820 resistor to limit the output swing (V
TTL gate with its so-called totem-pole output. The LT1715
is fabricated in a complementary bipolar process and the
output stage has a PNP driver that pulls the output nearly
all the way to the supply rail, even when sourcing 10mA.
Figure 8b shows a three resistor level translator for inter-
facing the LT1715 to ECL running off the same supply rail.
No pull-down on the output of the LT1715 is needed, but
pull-down R3 limits the V
needed because ECL inputs have both a minimum and
maximum V
values are given for both ECL interface types; in both cases
it is assumed that the LT1715 operates from the same
supply rail.
Figure 8c shows the case of translating to PECL from an
LT1715 powered by a 3V supply rail. Again, resistor values
are given for both ECL interface types. This time four re-
sistors are needed, although with 10KH/E, R3 is not needed.
In that case, the circuit resembles the standard TTL trans-
lator of Figure 8a, but the function of the new resistor, R4,
is much different. R4 loads the LT1715 output when high
so that the current flowing through R1 doesn’t forward
bias the LT1715’s internal ESD clamp diode. Although this
diode can handle 20mA without damage, normal
IH
specification for proper operation. Resistor
IH
seen by the PECL gate. This is
OH
) of the all-NPN
LT1715
11