AD5293 Analog Devices, AD5293 Datasheet - Page 7

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AD5293

Manufacturer Part Number
AD5293
Description
Digital Potentiometer
Manufacturer
Analog Devices
Datasheet

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Preliminary Technical Data
INTERFACE TIMING SPECIFICATIONS
V
Table 3.
Parameter
1
2
3
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
Maximum SCLK frequency is 50 MHz
R
DD
PULL_UP
/ V
= 2.2kΩ to V
SS
= ±15 V, V
t
t
t
t
t
t
t
t
OTP
t
t
t
t
t
t
t
t
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
2
3
3
3
3
3
3
LOGIC
LOGIC
= 2.7V to 5.5V, and −40°C < T
Unit
TBD(40)
1
TBD
TBD
TBD
TBD
TBD
TBD
125
20
10
10
15
13
5
5
0
Unit
ns max
µs max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs min
ns min
ns min
ns min
ns min
ns min
ns min
Figure 2. AD5293 Input Register Content
A
DD
< + 105°C. All specifications T
) and timed from a voltage level of (V
Rev. PrA | Page 7 of 15
Test Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK fall ignore
RDY rise to SYNC falling edge
RDY Low Time – RDAC Register write command execute time
RDY Low Time – RDAC Register read command execute time
SCLK rising edge to SDO valid
SCLK to SDO Data hold time
Power-on OTP restore time
SYNC rise to RDY fall time
MIN
IL
+ V
to T
IH
)/2.
MAX
, unless otherwise noted.
AD5293

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