AD5293 Analog Devices, AD5293 Datasheet - Page 10

• Manufacturer Part Number: AD5293
• Description: Digital Potentiometer
• Manufacturer: Analog Devices

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AD5293
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mnemonic
RESET
V
A
W
B
V
EXT_CAP
V
GND
DIN
SCLK
SYNC
SDO
RDY
SS
DD
LOGIC
Hardware reset pin. Sets the RDAC register to midscale. RESET is activated at the logic high transition. Tie RESET
to V
Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1µF
ceramic capacitors and 10 µF capacitors.
Terminal A of RDAC. V
Wiper terminal of RDAC. V
Terminal B of RDAC. V
Positive Power Supply. This pin should be decoupled with 0.1µF ceramic capacitors and 10 µF capacitors.
Connect a 1µF capacitor to EXT_CAP.
Logic Power Supply; 2.7V to 5.5V. This pin should be decoupled with 0.1µF ceramic capacitors and 10 µF
capacitors.
Ground Pin, Logic Ground Reference.
Serial Data Input. This part has a 16-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 50 MHz.
Falling edge Synchronisation signal.
This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift
register and data is transferred in on the falling edges of the following clocks. The selected DAC register is
updated on the rising edge of SYNC following the 16
cycle the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.
Serial Data Output. Open Drain Output requires external pull-up resistor. SDO can be used to clock data from
the serial register in daisy chain or readback mode.
Ready pin. Active-high open-drain output. Identifies the completion of a write or read operation to/from the
RDAC Register or read operation from memory Memory.
Description
LOGIC
if not used.
SS
SS
≤ V
≤ V
Figure 5. 14-pin TSSOP Pin Configuration
SS
B
A
≤ V
≤ V
≤ V
W
DD
DD
Rev. PrA | Page 10 of 15
≤ V
DD
th
clock cycle. If SYNC is taken high before the 16
Preliminary Technical Data
th
clock