MCS9845 MosChip Semiconductor, MCS9845 Datasheet - Page 9

• Manufacturer Part Number: MCS9845
• Description: PCI Dual UART
• Manufacturer: MosChip Semiconductor

Rev. 2.5
PCI Resource Allocation
PCI devices do not have “Hard-Wired” assignments for
memory or I/O Ports like ISA devices do. PCI devices
use “Plug & Play” to obtain the required resources
each time the system boots up. Each PCI device can
request up to six resource allocations. These can be
blocks of memory (RAM) or blocks of I/O Registers.
The size of each resource block requested can also
be specifi ed, allowing great fl exibility. Each of these
resource blocks is accessed by means of a Base-
Address-Register (BAR). As the name suggests, this
is a pointer to the start of the resource. Individual
registers are then addressed using relative offsets
from the Base-Address-Register contents.
important thing to note is: plugging the same PCI card
into different machines will not necessarily result in the
same addresses being assigned to it. For this reason,
software (drivers, etc.) must always obtain the specifi c
addresses for the device from the PCI System.
Each PCI device is assigned an entry in the PCI
System’s shared “Confi guration Space”. Every device
is allocated 256 Bytes in the Confi guration Space.
The fi rst 64 Bytes must follow the conventions of a
standard PCI Confi guration “Header”.
several pieces of information the device must present
in specifi c fi elds within the header to allow the PCI
System to properly identify it.
Vendor-ID, Device-ID and Class-Code. These three
fi elds should provide enough information to allow the
PCI System to associate the correct software driver
with the hardware device. Other fi elds can be used
to provide additional information to further refi ne the
needs and capabilities of the device.
As part of the Enumeration process (discovery of
which devices are present in the system) the Base-
Address-Registers are confi gured for each device.
The device tells the system how many registers (etc.)
it requires, and the system maps that number into the
system’s resource space, reserving them for exclusive
use by that particular device.
made that any two requests for resources will have
any predictable relationship to each other. Each PCI
System is free to use its own allocation strategy when
managing resources.
No guarantees are
These include the
There are
The
Multi-Function Devices
MosChip uses the Subsystem-ID fi eld to indicate how
many Serial Ports and Parallel Ports are provided
by the current implementation.
data in the Subsystem-ID fi eld, and stuffi ng only the
appropriate number of external components, the same
board could be used for products with either one or
two Ports. The least signifi cant Hexadecimal digit of
the Subsystem-ID fi eld indicates the number of Serial
Ports that are currently being provided by the device.
The next higher digit indicates the number of Parallel
Ports being provided. The table below shows several
different combinations and the types of Ports that
would be enabled. Some MosChip devices provide
Serial Ports, some provide Parallel Ports, and some
provide both types of Ports. This fi eld is used as an
aid to the software Drivers, allowing them to easily
determine how many of each Port type to confi gure.
This use of the term “Multi-Function Device” should
not be confused with the more generic use of that term
by the PCI System. Each “Function” within a “Unit”
(physical device) gets its own Confi guration Space
Header. MosChip’s devices do not need this extra
layer of complexity, the six Base Address Registers
provided by one PCI “Function” are more than
adequate to allocate all of the desired resources.
External EEPROM
Data is read from the EEPROM immediately after a
Hardware Reset, and the values obtained are used to
update the Confi guration before the PCI System fi rst
sees the device on the Bus. This allows a vendor to
substitute their own ID codes in place of the MosChip
codes for example. If no EEPROM is detected after
a Hardware Reset, MosChip’s default values for the
confi guration are provided by the chip itself.
Subsystem-ID
0001
0010
0012
PCI Dual UART with ISA Bridge
Parallel Ports
MCS9845
0
1
1
By changing the
Serial Ports
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