MCS9845 MosChip Semiconductor, MCS9845 Datasheet - Page 19

• Manufacturer Part Number: MCS9845
• Description: PCI Dual UART
• Manufacturer: MosChip Semiconductor

Rev. 2.5
Line Status Register (LSR)
The Line Status Register provides information
concerning the status of data transfers. The Line
Status Register is intended for read operations only.
Writing to this register is not recommended. Bits 1-4
are the error conditions that produce a Receiver Line
Status interrupt.
LSR Bit-0:
0 = No data in Receiver Holding Register or FIFO.
1 = Data Ready indicator for the receiver. This bit is
LSR Bit-1:
0 = Normal operation. No overrun error.
1 = Before the character in the Receiver Holding
LSR Bit-2:
0 = Normal operation. No parity error.
1 = The parity of the received character does not
LSR Bit-3:
0 = Normal operation. No framing error.
1 = The received character did not have a valid stop
set to 1 whenever a complete incoming character
has been received and transferred into the
Receiver Holding Register or the FIFO. It is reset
to 0 by reading all of the data in the Receiver
Holding Register or the FIFO.
Register was read, it was over written by the next
character transferred into the register. This bit
is reset every time the CPU reads the contents
of the Line Status Register. If FIFO mode data
continues to fi ll the FIFO beyond the trigger level,
an overrun error occurs only after the FIFO is
full and the next character has been completely
received in the shift register. An overrun error is
indicated as soon as it happens. The character
in the shift register is overwritten, but it is not
transferred to the FIFO.
match the parity selected in the Line Control
Register. This bit is reset every time the CPU
reads the contents of the Line Status Register.
In FIFO mode, this error is associated with
the particular character in the FIFO to which
it applies. This error is reported when its
associated character is at the top of the FIFO.
bit. This bit is reset every time the CPU reads
the contents of the Line Status Register. In FIFO
mode, this error is associated with the particular
LSR Bit-4:
0 = Normal operation.
1 = The receiver data input was held in the logic low
LSR Bit-5:
0 = At least one character is in the transmitter FIFO
1 = The Transmitter Holding Register is empty. The
LSR Bit-6:
0 = When either the Transmitter Holding Register or
1 = The Transmitter Holding Register and the
LSR Bit-7:
0 = In the 16C450 mode, this bit is always reset to 0.
1 = In the FIFO (16C550) mode, at least one parity,
character in the FIFO to which it applies. This
error is reported when its associated character
is at the top of the FIFO. An attempt to re-
synchronize is made after a framing error occurs.
It is assumed that the framing error is due to the
next start bit.
state for longer than a full word transmission
time. A full word transmission time is defi ned
as the total time to transmit the start, data,
parity, and stop bits. This bit is reset every time
the CPU reads the contents of the Line Status
Register. In FIFO mode, this error is associated
with the particular character in the FIFO to
which it applies. This error is reported when its
associated character is at the top of the FIFO.
When a break occurs, only one 0 character is
loaded into the FIFO.
or Transmitter Holding Register.
device is ready to accept a new character. If
the THRE interrupt is enabled when THRE is
set to 1, an interrupt is generated. THRE is set
to 1 when the last character in the Transmitter
Holding Register is transferred to the Transmitter
Shift Register.
the Transmitter Shift Register contains a data
character.
Transmitter Shift Register are both empty.
framing, or break error exists in the FIFO. It is
cleared when the microprocessor reads the LSR
and there are no subsequent errors in the FIFO.
PCI Dual UART with ISA Bridge
MCS9845
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Page 19