MCS9845 MosChip Semiconductor, MCS9845 Datasheet - Page 10

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MCS9845

Manufacturer Part Number
MCS9845
Description
PCI Dual UART
Manufacturer
MosChip Semiconductor
Datasheet

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Page 10
MCS9845
PCI Dual UART with ISA Bridge
PCI Confi guration Space Header
Default values for several key fi elds are shown in the table below.
Internal Address Select Confi guration
The MCS9845 uses two Base Address Registers for its UARTs, and four for the ISA Bridge.
These essentially act as internal “Chip Select” logic.
Registers are addressed by using one of the Base Addresses plus an offset.
Max Latency (00)
AD 31-23
BIST
Subsystem ID (0014)
0 (U1)
1 (U2)
2 (E3)
3 (E4)
4 (E5)
5 (E6)
BAR
Device ID (9845)
Base Address Register (BAR) 0 – “UART-A” (U1)
Base Address Register (BAR) 1 – “UART-B” (U2)
Base Address Register (BAR) 2 – “nCS3” (E3)
Base Address Register (BAR) 3 – “nCS4” (E4)
Base Address Register (BAR) 4 – “nCS5” (E5)
Base Address Register (BAR) 5 – “nCS6” (E6)
Status
Class Code (078000)
I/O Address Offset
Min Grant (00)
Header Type
AD 22-16
00-07
00-07
00-07
00-07
00-07
00-07
Reserved
Reserved
Reserved
Reserved
Interrupt Pin (01)
Latency Timer
Subsystem Vendor ID (1000)
AD 15-8
Vendor ID (9710)
Command
External Chip Select 3
External Chip Select 4
External Chip Select 5
External Chip Select 6
Revision ID (01)
Cache Size (08)
Interrupt Line
Function
UART-A
UART-B
AD 7-0
Offset (Hex)
0C
1C
2C
3C
00
04
08
10
14
18
20
24
28
30
34
38
www.DataSheet4U.com
Rev.
2.5

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