74LVT574PW,118 NXP Semiconductors, 74LVT574PW,118 Datasheet - Page 2

• Manufacturer Part Number: 74LVT574PW,118
• Description: IC OCTAL D TRANSP F-F 20TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVTr
• Type: D-Type Busr

Specifications of 74LVT574PW,118

• Package / Case: 20-TSSOP
• Function: Standard
• Output Type: Tri-State Non Inverted
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Frequency - Clock: 150MHz
• Delay Time - Propagation: 3.6ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 32mA, 64mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Circuits: 1
• Logic Family: LVT
• Logic Type: D-Type Edge Triggered Flip-Flop
• Polarity: Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 4.3 ns at 3.3 V
• High Level Output Current: - 32 mA
• Supply Voltage (max): 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 2.7 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4634-2; 74LVT574PW-T; 74LVT574PW-T; 935176370118

NXP Semiconductors
3. Ordering information
Table 1.
4. Functional diagram
74LVT_LVTH574_4
Product data sheet
Type number
74LVT574D
74LVTH574D
74LVT574DB
74LVTH574DB
74LVT574PW
74LVTH574PW
74LVT574BQ
Fig 1.
Fig 3.
CP
OE
Logic symbol
Logic diagram
Ordering information
D0
D
CP Q
Package
Temperature range Name
40 C to +85 C
40 C to +85 C
40 C to +85 C
40 C to +85 C
2
3
4
5
6
7
8
9
Q0
D0
D1
D2
D3
D4
D5
D6
D7
D1
D
CP Q
OE
CP
11
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna798
Q1
19
18
17
16
15
14
13
12
D2
SO20
SSOP20
TSSOP20
DHVQFN20
D
CP Q
Rev. 04 — 11 September 2008
Q2
D3
D
CP Q
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5
Fig 2.
Q3
D4
4.5
D
CP Q
74LVT574; 74LVTH574
IEC logic symbol
0.85 mm
Q4
D5
11
2
3
4
5
6
7
8
9
1
D
CP Q
3.3 V octal D-type flip-flop; 3-state
EN2
1D
C1
Q5
001aae466
D6
2
D
CP Q
19
18
17
16
15
14
13
12
© NXP B.V. 2008. All rights reserved.
Q6
D7
D
CP Q
Version
SOT163-1
SOT339-1
SOT360-1
SOT764-1
001aae467
Q7
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