TS68302MAB Atmel Corporation, TS68302MAB Datasheet - Page 35

• Manufacturer Part Number: TS68302MAB
• Description: 16-bit Communication Controller, 16-20 MHz
• Manufacturer: Atmel Corporation

68000/68008 Core
Overview
System Integration Block
(SIB)
IDMA Controller
Interrupt Controller
2117A–HIREL–11/02
The TS68302 allows operation either in the full 68000 mode with a 16-bit data bus or in
the 68008 mode with an 8-bit data bus.
The TS68302 has an SIB which simplifies the task of hardware and software design.
The IDMA controller eliminates the need for an external DMA controller on the system
board. In addition, there is an interrupt controller that can be used in a dedicated mode
to generate interrupt acknowledge signals without external logic. Similarly, the chip-
select signals and wait-state logic eliminate the need to generate these signals
externally.
The SIB includes the IDMA controller, interrupt controller, parallel I/O ports, dual-port
RAM, three timers, chip-select logic, clock generator, and system control.
The TS68302 has one IDMA channel and six serial DMA channels which operate con-
currently with other CPU operations. The IDMA can operate in different modes of data
transfer as programmed by the user. The six serial DMA channels for the three full-
duplex SCC channels are transparent to the user, implementing bus-cycle-stealing data
transfers controlled by the TS68302’s internal RISC controller. These six channels have
priority over the separate IDMA channels.
The IDMA controller can transfer data between any combination of memory and I/O
devices. In addition, data may be transferred in either byte or word quantities, and the
source and destination addresses may be either odd or even. Every IDMA cycle
requires between two and four bus cycles, depending on the address boundary and
transfer size. If both the source and destination addresses are even, the IDMA fetches
one word of data and then immediately deposits it. If either the source or destination
block begins on an odd boundary, the transfer takes more bus cycles.
The IDMA features are as follows:
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The interrupt controller, which manages the priority of internal and external interrupt
requests, generates a vector number during the CPU interrupt acknowledge cycle.
Nested interrupts are fully supported.
The interrupt controller receives requests from internal sources (INRQ interrupts) such
as the timers, the IDMA, the serial controllers, and the parallel I/O pins (port B). The
interrupt controller allows the masking of each INRQ interrupt source. When multiple
events within a peripheral can cause the interrupt, each of these events is also
maskable.
memory-memory, memory-peripheral, or peripheral-memory data transfers,
operation with data blocks located at even or odd addresses,
packing and unpacking of operands,
fast transfer rates: up to 4 MBps at 16 MHz with no wait states,
full support of all bus exceptions: halt, bus error, and retry,
flexible request generation
two address pointer registers and one counter register,
three I/O lines for externally requested data transfers,
asynchronous bus structure with 24-bit address and 8- to 16-bit data bus.
TS68302
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