TS68302MAB Atmel Corporation, TS68302MAB Datasheet - Page 30

• Manufacturer Part Number: TS68302MAB
• Description: 16-bit Communication Controller, 16-20 MHz
• Manufacturer: Atmel Corporation

Table 20. AC Electrical Specifications - GCI Timing
GCI supports the NORMAL mode and the GCI channel 0 (GCN0) in MUX mode. Normal mode uses 512 kHz clock rate
(256K bit rate). MUX mode uses 256 x n - 3068K bits/sec (clock rate is data rate x 2). The ratio CLK/L1CLK must be greater
than 2.5/1.
Notes:
30
Num.
280
281
282
280
281
282
283
284
285
286
287
288
289
290
291
292
293
1. The ratio CLK/L1CLK must be greater than 2.5/1.
2. Schmitt trigger used on input buffer.
3. Condition C
4. SDS1-SDS2 become valid after the L1CLK rising edge or L1SY1, whichever is later.
5. See Figure 24.
TS68302
Parameter
L1CLK GCI clock frequency (normal mode)
L1CLK clock period normal mode
L1CLK width low/high normal mode
L1CLK rise/fall time normal mode
L1CLK (GCI clock) period (MUX mode)
L1CLK clock period MUX mode
L1CLK width low/high MUX mode
L1CLK rise/fall time MUX mode
L1SY1 sync setup time to L1CLK falling edge
L1SY1 sync hold time from L1CLK falling edge
L1T x D active delay (from L1CLK rising edge)
L1T x D active delay (from L1SY1 rising edge)
L1R x D setup time to L1CLK rising edge
L1R x D hold time from L1CLK rising edge
Time between successive L1SY1 in normal mode
SDS1-SDS2 active delay from L1CLK riding edge
SDS1-SDS2 active delay from L1SY1 rising edge
SDS1-SDS2 inactive delay from L1CLK falling edge
GCIDCL (GCI Data clock) active delay
L
= 150 pF. L1T x D becomes valid after the L1CLK rising edge or L1SY1, whichever is later.
(2)
(1)
(2)
(1)
SCIT mode
(1)
(1)
(5)
(3)
(3)
f = 16.67 MHz
(4)
(4)
1800
Min
840
150
192
55
30
50
20
50
64
10
10
10
0
0
0
-
-
6.668
2100
1450
Max
512
100
100
90
90
90
50
-
-
2117A–HIREL–11/02
L1CLK
L1CLK
MHz
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns