TS68302MAB Atmel Corporation, TS68302MAB Datasheet - Page 17

• Manufacturer Part Number: TS68302MAB
• Description: 16-bit Communication Controller, 16-20 MHz
• Manufacturer: Atmel Corporation

Figure 9. Bus Arbitration Timing Diagram
Note:
Table 9. AC Electrical Specifications - DMA (see Figure 10) f = 16.67 MHz
Notes:
2117A–HIREL–11/02
Num.
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
STROBES
AND R/W
BGACK
Setup time to the clock (#47) for the asynchronous inputs BERR, BGACK, BR, DTACK, and IPL2-IPL0 guarantees their recog-
nition at the next falling edge of the clock.
1. DREQ is sampled on the falling edge of CLK in cycle steal and burst modes.
2. If #80 is satisfied for DREQ, #81 may be ignored.
3. BR will not be asserted while AS, HALT, or BERR is asserted.
4. Specifications are for DISABLE CPU mode only.
CLKO
BR
BG
Symbol
t
t
t
t
t
t
REQLBRL
t
t
t
t
CLBKLAL
t
t
BRHBGH
t
t
t
t
CHACKL
CLACKH
t
BKLBRZ
ABHBKL
BGLBKL
DNLTCH
REQASI
t
CHBKH
CHBRL
CHBRZ
CHBKL
CHDNL
CLDNZ
CLBKZ
REQL
Parameter
DREQ asynchronous setup time
DREQ width low
DREQ low to BR low
Clock high to BR low
Clock high to BR high impedance
BGACK low to BR high impedance
Clock high to BGACK low
AS and BGACK high (the latest one) to BGACK low (when
BG is asserted)
AS low to BGACK low (no other bus master)
BR high impedance to BG high
Clock on which BGACK low to clock on which AS low
Clock high to BGACK high
Clock low to BGACK high impedance
Clock high to DACK low
Clock high to DACK high
Clock high to DONE low (output)
Clock low to DONE high impedance
DONE input low to clock high (asynchronous setup)
35
33
(2)
(3)(4)
(3)(4)
38
(3)(4)
(1)
(3)(4)
37
(3)(4)
46
34
37A
(3)(4)
39
47
Min
1.5
15
30
15
2
0
2
36
Max
+ 30
+ 30
2.5
2.5
30
30
30
30
15
30
30
30
30
2
2
TS68302
57 57A
58 58A
Unit
clk
clk
clk
clk
clk
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
17