AD9518-2 Analog Devices, Inc., AD9518-2 Datasheet - Page 52

• Manufacturer Part Number: AD9518-2
• Description: 6-output Clock Generator With Integrated 2.2 Ghz Vco
• Manufacturer: Analog Devices, Inc.

Reg.
Addr
(Hex) Bit(s) Name
18
19
19
19
1A
1A
AD9518-2
<0>
<7:6> R, A, B
<5:3> R Path Delay <5:3> R Path Delay (see Table 2).
<2:0> N Path Delay <2:0> N Path Delay (see Table 2).
<6>
<5:0> LD Pin
VCO Cal
Now
Counters
SYNC Pin
Reset
Reference
Frequency
Monitor
Threshold
Control
Description
Bit used to initiate the VCO calibration. This bit must be toggled from 0 to 1 in the active registers. The sequence
to initiate a calibration is: program to 0, followed by an update bit (0x232<0>); then program to 1, followed by
another update bit (0x232<0>). This sequence gives complete control over when the VCO calibration occurs
relative to the programming of other registers that can impact the calibration.
<7>
0
0
1
1
Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect
the VCO frequency monitor’s detection threshold (see Table 15, REF1, REF2, and VCO Frequency Status Monitor).
<6> = 0; frequency valid if frequency is above the higher frequency threshold.
<6> = 1; frequency valid if frequency is above the lower frequency threshold.
Selects the signal that is connected to the LD pin.
<5> <4> <3>
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
<6>
0
1
0
1
0
0
0
0
0
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
Action
Do nothing on SYNC (default).
Asynchronous reset.
Synchronous reset.
Do nothing on SYNC.
<2>
0
0
0
0
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
X
<1> <0>
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Rev. 0 | Page 52 of 64
Level or
Dynamic
Signal
LVL
DYN
DYN
HIZ
CUR
LVL
LVL
DYN
DYN
DYN
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
DYN
DYN
DYN
DYN
Signal at LD Pin
Digital lock detect (high = lock, low = unlock).
P-channel, open-drain lock detect (analog lock detect).
N-channel, open-drain lock detect (analog lock detect).
High-Z LD pin.
Current source lock detect (110 μA when DLD is true).
Ground (dc); for all other cases of 0XXXXX not specified.
The selections that follow are the same as REFMON.
Ground (dc).
REF1 clock (differential reference when in differential mode).
REF2 clock (not available in differential mode).
Selected reference to PLL (differential reference when in
differential mode).
Unselected reference to PLL (not available in differential mode).
Status of selected reference (status of differential reference);
active high.
Status of unselected reference (not available in differential
mode); active high.
Status of REF1 frequency (active high).
Status of REF2 frequency (active high).
(Status of REF1 frequency) AND (status of REF2 frequency).
(DLD) AND (status of selected reference) AND (status of VCO).
Status of VCO frequency (active high).
Selected reference (low = REF1, high = REF2).
Digital lock detect (DLD); active high.
Holdover active (active high).
Not available—do not use.
VS (PLL supply).
REF1 clock (differential reference when in differential mode).
REF2 clock (not available in differential mode).
Selected reference to PLL (differential reference when in
differential mode).
Unselected reference to PLL (not available when in differential
mode).