AD9518-2 Analog Devices, Inc., AD9518-2 Datasheet - Page 38

• Manufacturer Part Number: AD9518-2
• Description: 6-output Clock Generator With Integrated 2.2 Ghz Vco
• Manufacturer: Analog Devices, Inc.

AD9518-2
Synchronization of the outputs is executed in several ways:
• The SYNC pin is forced low and then released (manual SYNC).
• By setting and then resetting any one of the following three
• Synchronization of the outputs can be executed as part of the
• The RESET pin is forced low and then released (chip reset).
• The PD pin is forced low and then released (chip power-down).
• Whenever a VCO calibration is completed, an internal SYNC
SYNC PIN
INPUT TO CHANNEL DIVIDER
bits: the soft SYNC bit (0x230<0>), the soft reset bit
(0x00<5> [mirrored]), or the power-down distribution
reference bit (0x230<1>).
chip power-up sequence.
signal is automatically asserted at the beginning and released
upon the completion of a VCO calibration.
INPUT TO VCO DIVIDER
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT OF
Figure 39. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input
1
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
2
3
CHANNEL DIVIDER OUTPUT STATIC
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The most common way to execute the SYNC function is to use
the SYNC pin to execute a manual synchronization of the
outputs. This requires a low-going signal on the SYNC pin,
which is held low and then released when synchronization is
desired. The timing of the SYNC operation is shown in Figure 39
(using VCO divider) and Figure 40 (VCO divider not used).
There is an uncertainty of up to one cycle of the clock at the
input to the channel divider due to the asynchronous nature of
the SYNC signal with respect to the clock edges inside the
AD9518. The delay from the SYNC rising edge to the beginning of
synchronized output clocking is between 14 and 15 cycles of
clock at the channel divider input, plus either one cycle of the VCO
divider input (see Figure 39), or one cycle of the channel divider
input (see Figure 40), depending on whether the VCO divider is
used. Cycles are counted from the rising edge of the signal.
Another common way to execute the SYNC function is by
setting and resetting the soft SYNC bit at 0x230<0> (see Table 42
through Table 48 for details). Both setting and resetting of the
soft SYNC bit requires an update all registers (0x232<0> = 1)
operation to take effect.
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9
10
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12
13
14
1
OUTPUT CLOCKING
CHANNEL DIVIDER