AD9518-2 Analog Devices, Inc., AD9518-2 Datasheet - Page 32

• Manufacturer Part Number: AD9518-2
• Description: 6-output Clock Generator With Integrated 2.2 Ghz Vco
• Manufacturer: Analog Devices, Inc.

AD9518-2
Holdover
The AD9518 PLL has a holdover function. Holdover is
implemented by putting the charge pump into a high impedance
state. This is useful when the PLL reference clock is lost.
Holdover mode allows the VCO to maintain a relatively
constant frequency even though there is no reference clock.
Without this function, the charge pump is placed into a
constant pump-up or pump-down state, resulting in a massive
VCO frequency shift. Because the charge pump is placed in a
high impedance state, any leakage that occurs at the charge
pump output or the VCO tuning node causes a drift of the
VCO frequency. This can be mitigated by using a loop filter
that contains a large capacitive component because this drift is
limited by the current leakage induced slew rate (I
VCO control voltage.
Both a manual holdover, using the SYNC pin, and an automatic
holdover mode are provided. To use either function, the holdover
function must be enabled (0x1D<0> and 0x1D<2>).
[Note that the VCO cannot be calibrated with the holdover
enabled because the holdover resets the N divider during
calibration, which prevents proper calibration. Disable holdover
before issuing a VCO calibration.]
Manual Holdover Mode
A manual holdover mode can be enabled that allows the user to
place the charge pump into a high impedance state when the
SYNC pin is asserted low. This operation is edge sensitive, not
level sensitive. The charge pump immediately enters a high
impedance state. To take the charge pump out of a high
impedance state, take the SYNC pin high. The charge pump
then leaves the high impedance state synchronously with the
next PFD rising edge from the reference clock. This prevents
extraneous charge pump events from occurring during the time
between SYNC going high and the next PFD event. This also
means that the charge pump stays in a high impedance state as
long as there is no reference clock present.
The B-counter (in the N divider) is reset synchronously with the
charge pump leaving the high impedance state on the reference
path PFD event. This helps align the edges out of the R and N
dividers for faster settling of the PLL. Because the prescaler is
not reset, this feature works best when the B and R numbers are
close because this results in a smaller phase difference for the
loop to settle out.
When using this mode, the channel dividers should be set to
ignore the SYNC pin (at least after an initial SYNC event). If the
dividers are not set to ignore the SYNC pin, any time SYNC is
taken low to put the part into holdover, the distribution outputs
turn off.
LEAK
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Automatic/Internal Holdover Mode
When enabled, this function automatically puts the charge
pump into a high impedance state when the loop loses lock.
The assumption is that the only reason the loop loses lock is due
to the PLL losing the reference clock; therefore, the holdover
function puts the charge pump into a high impedance state to
maintain the VCO frequency as close as possible to the original
frequency before the reference clock disappears.
A flow chart of the automatic/internal holdover function
operation is shown in Figure 36.
The holdover function senses the logic level of the LD pin as a
condition to enter holdover. The signal at LD can be from the
DLD, ALD, or current source LD mode. It is possible to disable
the LD comparator (0x1D<3>), which causes the holdover
function to always sense LD as high. If DLD is used, it is
possible for the DLD signal to chatter some while the PLL is
reacquiring lock. The holdover function may retrigger, thereby
preventing the holdover mode from terminating. Use of the
current source lock detect mode is recommended to avoid this
situation (see the Current Source Digital Lock Detect section).
HIGH IMPEDANCE
HIGH IMPEDANCE
WHEN DLD WENT
LD PIN == HIGH
CHARGE PUMP
CHARGE PUMP
EDGE AT PFD?
PLL ENABLED
DLD == HIGH
DLD == LOW
REFERENCE
RELEASE
LOW?
Figure 36. Flow Chart of Automatic/Internal Holdover Mode
WAS
YES
YES
YES
YES
YES
NO
NO
NO
NO
YES
LOOP OUT OF LOCK. DIGITAL LOCK
DETECT SIGNAL GOES LOW WHEN THE
LOOP LEAVES LOCK AS DETERMINED
BY THE PHASE DIFFERENCE AT THE
INPUT OF THE PFD.
ANALOG LOCK DETECT PIN INDICATES
LOCK WAS PREVIOUSLY ACHIEVED.
(0x1D<3> = 1: USE LD PIN VOLTAGE
WITH HOLDOVER.
0x1D<3> = 0: IGNORE LD PIN VOLTAGE,
TREAT LD PIN AS ALWAYS HIGH.)
CHARGE PUMP IS MADE
HIGH IMPEDANCE.
PLL COUNTERS CONTINUE
OPERATING NORMALLY.
CHARGE PUMP REMAINS HIGH
IMPEDANCE UNTIL THE REFERENCE
HAS RETURNED.
TAKE CHARGE PUMP OUT OF
HIGH IMPEDANCE. PLL CAN
NOW RESETTLE.
WAIT FOR DLD TO GO HIGH. THIS TAKES
5 TO 255 CYCLES (PROGRAMMING OF THE DLD
DELAY COUNTER) WITH THE REFERENCE AND
FEEDBACK CLOCKS INSIDE THE LOCK WINDOW AT
THE PFD. THIS ENSURES THAT THE HOLDOVER
FUNCTION WAITS FOR THE PLL TO SETTLE AND LOCK
BEFORE THE HOLDOVER FUNCTION CAN BE
RETRIGGERED.