AD9639 Analog Devices, Inc., AD9639 Datasheet - Page 23

• Manufacturer Part Number: AD9639
• Description: Quad, 12-bit, 170 Msps/210 Msps Serial Output 1.8 V Adc
• Manufacturer: Analog Devices, Inc.

Initial Synchronization
The serial interface must synchronize to the frame boundaries
before data can be properly decoded. The JESD204 standard has
a synchronization routine to identify the frame boundary. The
PGMx pins are used as SYNC pins by default. When the SYNC
pin is taken low for at least two clock cycles, the AD9639 enters
the synchronization mode. The AD9639 transmits the K28.5
comma symbol until the receiver can identify the frame boundary.
The receiver should then deassert the sync signal (take SYNC
high) and the ADC begins transmitting real data. The first non-
K28.5 symbol is the MSB symbol of the 12-bit data.
Table 8. Variables Used in Receiver State Machine
Variable
ICOUNTER
/INVALID/
/K28.5/
KCOUNTER
SYNC_REQUEST
/VALID/
VCOUNTER
SYNC_REQUEST = ‘0’;
KCOUNTER = ‘0’;
IF /INVALID/ THEN
ELSE IF /VALID/ THEN
END IF;
VCOUNTER = VCOUNTER + ‘1’;
ICOUNTER = ICOUNTER + ‘1’;
VCOUNTER = ‘0’;
Description
Counter used in the CHECK phase to count the number of invalid symbols.
Asserted by receiver to indicate that the current symbol is an invalid symbol given the current running disparity.
Asserted when the current symbol corresponds to the K28.5 control character.
Counter used in the INIT phase to count the number of valid K28.5 symbols.
Asserted by receiver when loss of code group synchronization is detected.
Asserted by receiver to indicate that the current symbol is a valid symbol given the current running disparity.
Counter used in the CHECK phase to count the number of successive valid symbols.
ICOUNTER = ‘0’;
VCOUNTER = ‘0’;
SYNC_REQUEST = ‘1’;
IF /K28.5/ AND /VALID/ THEN
ELSE
END IF;
KCOUNTER = KCOUNTER + ‘1’;
KCOUNTER = ‘0’;
VCOUNTER < 4 AND ICOUNTER < 3
KCOUNTER < 4
ICOUNTER = 3
Figure 55. Receiver State Machine
CHECK
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VCOUNTER = 4
To minimize skew and time misalignment between each channel
of the digital outputs, the following actions should be taken to
ensure that each channel data frame is within ±1 clock cycle of
the sample clock. For some receiver logic, this is not required.
1.
2.
3.
/INVALID/
RESET
KCOUNTER = 4
INIT
Full power-down through external PDWN pin.
Chip reset via external RESET pin.
Power-up by releasing external PDWN pin.
DATA
ICOUNTER = ‘0’;
VCOUNTER = ‘0’;
/VALID/
AD9639