ST62T42B ST Microelectronics, ST62T42B Datasheet - Page 20

• Manufacturer Part Number: ST62T42B
• Description: 8-BIT OTP/EPROM MCU WITH LCD DRIVER / EEPROM AND A/D CONVERTER
• Manufacturer: ST Microelectronics

ST62T42B/E42B
RESETS (Cont’d)
3.2.3 Watchdog Reset
The MCU provides a Watchdog timer function in
order to ensure graceful recovery from software
upsets. If the Watchdog register is not refreshed
before an end-of-count condition is reached, the
internal reset will be activated. This, amongst oth-
er things, resets the watchdog counter.
The MCU restarts just as though the Reset had
been generated by the RESET pin, including the
built-in stabilisation delay period.
3.2.4 Application Notes
No external resistor is required between V
the Reset pin, thanks to the built-in pull-up device.
The POR circuit operates dynamically, in that it
triggers MCU initialization on detecting the rising
edge of V
of 2 volts, but the actual value of the detected
threshold depends on the way in which V
The POR circuit is NOT designed to supervise
static, or slowly rising or falling V
3.2.5 MCU Initialization Sequence
When a reset occurs the stack is reset, the PC is
loaded with the address of the Reset Vector (locat-
ed in program ROM starting at address 0FFEh). A
jump to the beginning of the user program must be
coded at this address. Following a Reset, the In-
terrupt flag is automatically set, so that the CPU is
in Non Maskable Interrupt mode; this prevents the
Figure 12. Reset Block Diagram
20/68
20
RESET
DD
. The typical threshold is in the region
V
DD
WATCHDOG RESET
POWER
300k
2.8k
ON RESET
DD
.
f
OSC
DD
DD
rises.
and
initialisation routine from being interrupted. The in-
itialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
mode and enable interrupts. If no pending interrupt
is present at the end of the initialisation routine, the
MCU will continue by processing the instruction
immediately following the RETI instruction. If, how-
ever, a pending interrupt is present, it will be serv-
iced.
Figure 11. Reset and Interrupt Processing
RESET
VECTOR
RESET
INITIALIZATION
ROUTINE
CK
RESET
COUNTER
RESET
RETI
JP
JP:2 BYTES/4 CYCLES
RETI: 1 BYTE/2 CYCLES
ST6
INTERNA L
RESET
VA0200B
VA00181