CY7C4255-15AXC Cypress Semiconductor Corp, CY7C4255-15AXC Datasheet - Page 7

• Manufacturer Part Number: CY7C4255-15AXC
• Description: IC SYNC FIFO MEM 8KX18 64LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4255-15AXC

• Function: Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 8Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 45mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Waveforms
Document #: 38-06004 Rev. *E
Notes
15. t
16. t
between the rising edge of RCLK and the rising edge of WCLK is less than t
between the rising edge of WCLK and the rising edge of RCLK is less than t
Q
SKEW1
SKEW2
D
0
0
WCLK
WCLK
RCLK
RCLK
WEN
–D
–Q
WEN
REN
REN
OE
FF
EF
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF goes HIGH during the current clock cycle. It the time
17
17
t
ENS
t
OLZ
t
SKEW1
t
ENH
t
[15]
t
CLKH
CLKH
t
t
t
WFF
A
REF
t
OE
Figure 3. Write Cycle Timing
Figure 4. Read Cycle Timing
t
t
CLK
CLK
t
SKEW2
NO OPERATION
[16]
t
DS
t
CLKL
t
CLKL
t
ENS
SKEW1
SKEW2
, then FF may not change state until the next WCLK rising edge.
, then EF may not change state until the next RCLK rising edge.
CY7C4255, CY7C4265, CY7C4265A
t
VALID DATA
DH
t
ENH
t
REF
t
WFF
t
OHZ
NO OPERATION
Page 7 of 23
[+] Feedback
[+] Feedback