CY7C4255-15AXC Cypress Semiconductor Corp, CY7C4255-15AXC Datasheet - Page 17

• Manufacturer Part Number: CY7C4255-15AXC
• Description: IC SYNC FIFO MEM 8KX18 64LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4255-15AXC

• Function: Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 8Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 45mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Width Expansion Configuration
The CY7C4255/65/65A can be expanded in width to provide word widths greater than 18 in increments of 18. During width expansion
mode all control line inputs are common and all flags are available. Empty (Full) flags should be created by ANDing the Empty (Full)
flags of every FIFO; the PAE and PAF flags can be detected from any one device. This technique avoids reading data from, or writing
data to the FIFO that is “staggered” by one clock cycle due to the variations in skew between RCLK and WCLK.
strates a 36-word width by using two CY7C4255/65/65As.
Depth Expansion Configuration
(with Programmable Flags)
The CY7C4255/65/65A can easily be adapted to applications requiring more than 8192/16384 words of buffering.
Depth Expansion using three CY7C42X5s. Maximum depth is limited only by signal loading. Follow these steps:
Document #: 38-06004 Rev. *E
FULL FLAG (FF)
1. The first device must be designated by grounding the First Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device.
4. The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next device.
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in the Depth Expansion Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by ORing together these respective flags for monitoring. The composite
DATA IN (D)
PAE and PAF flags are not precise.
PROGRAMMABLE(PAE)
HALF FULL FLAG (HF)
Figure 21. Block Diagram of 8K x18/16K x 18 Synchronous FIFO Memory Used in a Width Expansion Configuration
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
36
18
FF
RESET (RS)
7C4255
7C4265
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
EF
FIRST LOAD (FL)
18
18
FF
CY7C4255, CY7C4265, CY7C4265A
RESET (RS)
7C4255
7C4265
EF
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAF)
18
DATA OUT (Q)
EMPTY FLAG (EF)
Figure 21
Figure 22
36
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