BU9889GUL-W Rohm, BU9889GUL-W Datasheet - Page 7

• Manufacturer Part Number: BU9889GUL-W
• Description: WL-CSP EEPROM family I2C BUS
• Manufacturer: Rohm

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BU9889GUL-W
www.rohm.com
2
C BUS communication
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master
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○Start condition (start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is
○Stop condition (stop bit recognition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・The device (this IC at slave address input of write command, read command, and µ-COM at data output of read
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal) (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.
・When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side, this IC
○Device addressing
・Following a START condition, the master output the slave address to be accessed.
・The most significant four bits of the slave address are the “device type indentifier,” for this device it is fixed as “1010”.
・The next bit (device address) identify the specified device on the bus. The device address is defined by the state of A2
・The next two bits (P1, P0) are used by the master to select four 256 word page of memory.
・The last bit of the stream (R/W … READ/WRITE) determines the operation to be performed. When set to “1”, a read
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and acknowledge is always required after each byte.
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serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by addresses peculiar to devices.
EEPROM becomes “slave”. And the device that outputs data to bus during data communication is called “transmitter”,
and the device that receives data is called “receiver”.
'HIGH' is necessary.
satisfied, any command is executed.
and slave, the device (µ-COM at slave address input of write command, read command, and this IC at data output of
read command) at the transmitter (sending) side releases the bus after output of 8bit data.
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes
stop condition (stop bit), and ends read action. And this IC gets in standby status.
input pin. This IC works only when the device address inputted from SDA pin correspond to the state of A2 input pin.
Using this address scheme, up to two devices may be connected to the bus.
operation is selected ; when set to “0”, a write operation is selected.
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2
2
C BUS data communication
C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and
1 0 1 0
P1, P0 set to “0” “0” ･･･ 1page (000～0FF)
P1, P0 set to “0” “1” ･･･ 1page (100～1FF)
P1, P0 set to “1” “0” ･･･ 1page (200～2FF)
P1, P0 set to “1” “1” ･･･ 1page (300～3FF)
R/W set to “0” ･･･ WRITE (including word address input of Random Read)
SDA
SCL
START
condition
R/W set to “1” ･･･ READ
S
A2
ADDRESS
1-7
R/W
8
Fig.31 Data transfer timing
ACK
9
P1
1-7
DATA
7/17
8
ACK
9
P0
1-7
DATA
8
ACK
9
R/W
condition
STOP
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2010.01 - Rev.A
Technical Note