BU9889GUL-W Rohm, BU9889GUL-W Datasheet - Page 3

• Manufacturer Part Number: BU9889GUL-W
• Description: WL-CSP EEPROM family I2C BUS
• Manufacturer: Rohm

●Sync data input/output timing
© 2010 ROHM Co., Ltd. All rights reserved.
BU9889GUL-W
www.rohm.com
SCL
SDA
SCL
SDA
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
(Output)
WRITE DATA(n)
(Input)
SCL
SDA
(入力)
SDA
(出力)
tSU:STA
Fig.1-(b) Start - stop bit timing
Fig.1-(a) Sync data input / output timing
tHD:STA
D0
tBUF
Fig.1-(c) Write cycle timing
tHD:STA
ACK
START BIT
CONDITION
tR
STOP
tSU:DAT
tPD
tF
t
tSU:STO
WR
tLOW
CONDITION
tHIGH
START
tDH
tHD:DAT
STOP BIT
3/17
SCL
SDA
WP
○At write execution, in the area from the D0 taken clock rise of the first DATA(1),
○By setting WP "HIGH" in the area, write can be cancelled.
to tWR, set WP= 'LOW'.
When it is set WP = 'HIGH' during tWR, write is forcibly ended, and data of address under
access is not guaranteed, therefore write it once again.
SCL
SDA
WP
D1
DATA(1)
tSU：WP
D1
D0
DATA(1)
Fig.1-(d) WP timing at write execution
D0
ACK
Fig.1-(e) WP timing at write cancel
ACK
DATA(n)
tHIGH:WP
DATA(n)
ACK
Stop condition
ストップコンディション
ACK
ｔWR
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tWR
2010.01 - Rev.A
Technical Note
tWR
ｔHD：WP