CS8405A Cirrus Logic, CS8405A Datasheet - Page 34

• Manufacturer Part Number: CS8405A
• Description: 96 KHZ DIGITAL AUDIO INTERFACE TRANSMITTER
• Manufacturer: Cirrus Logic

15. APPENDIX B: CHANNEL STATUS
The CS8405A has a comprehensive channel status
(C) and user (U) data buffering scheme which al-
lows the user to manage the C and U data through
the control port.
15.1 AES3 Channel Status(C) Bit
The CS8405A contains sufficient RAM to store a
full block of C data for both A and B channels
(192x2 = 384 bits), and also 384 bits of U informa-
tion. The user may read from or write to these RAM
buffers through the control port.
The CS8405A manages the flow of channel status
data at the block level, meaning that entire blocks
of channel status information are buffered at the in-
put, synchronized to the output timebase, and then
transmitted. The buffering scheme involves a cas-
cade of 2 block-sized buffers, named E and F, as
shown in Figure 14. The MSB of each byte repre-
sents the first bit in the serial C data stream. For ex-
ample, the MSB of byte 0 (which is at control port
address 32) is the consumer/professional bit for
channel status block A.
The E buffer is accessible from the control port, al-
lowing read and writing of the C data. The F buffer
is used as the source of C data for the AES3 trans-
mitter. The F buffer accepts block transfers from
the E buffer.
34
Figure 14. Channel Status Data Buffer Structure
AND USER DATA BUFFER
MANAGEMENT
8 -b its
Management
A
C on tro l Po rt
w o rd s
E
8 -b its
2 4
B
Tra nsm it
D ata
Buffer
F
To
AES3
Tra nsm itte r
15.1.1 Accessing the E buffer
The user can monitor the data being transferred by
reading the E buffer, which is mapped into the reg-
ister space of the CS8405A, through the control
port. The user can modify the data to be transmitted
by writing to the E buffer.
The user can configure the interrupt enable register
to cause interrupts to occur whenever “E to F” buff-
er transfers occur. This allows determination of the
allowable time periods to interact with the E buffer.
Also provided is an “E to F” inhibit bit. The “E to
F” buffer transfer is disabled whenever the user sets
this bit. This may be used whenever “long” control
port interactions are occurring.
A flowchart for reading and writing to the E buffer
is shown in Figure 15. For writing, the sequence
starts after a E to F transfer, which is based on the
output timebase.
If the channel status block to transmit indicates
PRO mode, then the CRCC byte is automatically
calculated by the CS8405A, and does not have to
be written into the last byte of the block by the host
microcontroller. This is also true if the channel sta-
tus data is entered serially through the COPY/C pin
when the part is in hardware mode.
Figure 15. Flowchart for Writing the E Buffer
E to F interrupt occurs
Return
Optionally set E to F inhibit
If set, clear E to F inhibit
Wait for E to F transfer
Write E data
CS8405A
DS469PP4