CS8405A Cirrus Logic, CS8405A Datasheet - Page 3

• Manufacturer Part Number: CS8405A
• Description: 96 KHZ DIGITAL AUDIO INTERFACE TRANSMITTER
• Manufacturer: Cirrus Logic

LIST OF FIGURES
DS469PP4
9. PIN DESCRIPTION - SOFTWARE MODE ............................................................................. 24
10. HARDWARE MODE ............................................................................................................. 26
11. PIN DESCRIPTION - HARDWARE MODE .......................................................................... 28
12. APPLICATIONS ................................................................................................................... 30
13. PACKAGE DIMENSIONS .................................................................................................. 31
14. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER COMPONENTS ...... 33
15. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT ........... 34
Figure 1. Audio Port Master Mode Timing ...................................................................................... 6
Figure 2. Audio Port Slave Mode and Data Input Timing................................................................ 6
Figure 3. SPI Mode timing............................................................................................................... 7
Figure 4. Two-Wire Mode timing ..................................................................................................... 8
Figure 5. Recommended Connection Diagram for Software Mode ................................................ 9
Figure 6. Serial Audio Input Example Formats ............................................................................. 11
Figure 7. AES3 Transmitter Timing for C, U and V pin input data ................................................ 13
Figure 8. Control Port Timing in SPI Mode ................................................................................... 14
Figure 9. Control Port Timing in Two-Wire Mode.......................................................................... 15
Figure 10. Hardware Mode ........................................................................................................... 26
Figure 11. Professional Output Circuit .......................................................................................... 33
Figure 12. Consumer Output Circuit ............................................................................................. 33
Figure 13. TTL/CMOS Output Circuit............................................................................................ 33
Figure 14. Channel Status Data Buffer Structure.......................................................................... 34
Figure 15. Flowchart for Writing the E Buffer ................................................................................ 34
8.9 Interrupt 1 Mode MSB (Ah) and Interrupt 1 Mode LSB(Bh).............................................. 21
8.10 Interrupt 2 Mask (Ch)...................................................................................................... 21
8.11 Interrupt 2 Mode MSB (Dh) and Interrupt Mode 2 LSB(Eh) ........................................... 22
8.12 Channel Status Data Buffer Control (12h) ...................................................................... 22
8.13 User Data Buffer Control (13h) ....................................................................................... 23
8.14 Channel Status bit or User bit Data Buffer (20h - 37h) ................................................... 23
8.15 CS8405A I.D. and Version Register (7Fh) (Read Only) ................................................. 23
10.1 Channel Status, User and Validity Data ........................................................................ 26
10.2 Serial Audio Port Formats ............................................................................................. 26
12.1 Reset, Power Down and Start-up .................................................................................. 30
12.2 ID Code and Revision Code .......................................................................................... 30
12.3 Power Supply, Grounding, and PCB layout ................................................................... 30
12.4 Synchronization of Multiple CS8405As ......................................................................... 30
12.4 ORDERING INFORMATION ......................................................................................... 30
14.1 AES3 Transmitter External Components ....................................................................... 33
14.2 Isolating Transformer Requirements ............................................................................. 33
15.1 AES3 Channel Status(C) Bit Management .................................................................... 34
15.2 AES3 User (U) Bit Management .................................................................................... 35
15.1.1 Accessing the E buffer ...................................................................................... 34
15.1.2 Serial Copy Management System (SCMS) ....................................................... 35
15.1.3 Channel Status Data E Buffer Access .............................................................. 35
15.2.1 Mode 1: Transmit All Zeros ............................................................................... 35
15.2.2 Mode 2: Block Mode ......................................................................................... 35
CS8405A
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