CA3338 Intersil Corporation, CA3338 Datasheet - Page 6

• Manufacturer Part Number: CA3338
• Description: CMOS Video Speed/ 8-Bit/ 50 MSPS/ R2R D/A Converters
• Manufacturer: Intersil Corporation

Dynamic Characteristics
Keeping the full-scale range (V
possible gives the best linearity and lowest “glitch” energy
(referred to 1V). This provides the best “P” and “N” channel
gate drives (hence saturation resistance) and propagation
8 DATA BITS
0
FIGURE 4. D/A INTEGRAL AND DIFFERENTIAL LINEARITY
GROUND
00
DIGITAL
NOTES:
Oscilloscope Display
Match 93 Cable
Match 75 Cable
Match 50 Cable
2. V
3. All drawn capacitors are 0.1 F multilayer ceramic/4.7 F tantalum.
4. Dashed connections are for unipolar operation. Solid connection are for bipolar operation.
CLOCK
+5V
OUT(P-P)
= IDEAL TRANSFER CURVE
= ACTUAL TRANSFER CURVE
A
FUNCTION
ERROR
is approximate, and will vary as R
C
1-7, 9
A = IDEAL STEP SIZE (1/255 OF FULL
B - A = +DIFFERENTIAL LINEARITY ERROR
C - A = -DIFFERENTIAL LINEARITY ERROR
B
INPUT CODE
SCALE -“0” SCALE VOLTAGE)
+
STRAIGHT LINE
FROM “0” SCALE
TO FULL SCALE
VOLTAGE
15
16
14
8
REF
LE
D0 - D7
V
COMP
V
DD
SS
+ - V
INTEGRAL LINEARITY
CONNECTOR
CA3338
ERROR (SHOWN -)
Probe Tip
FIGURE 5. CA3338 DYNAMIC TEST CIRCUIT
BNC
BNC
BNC
REF
V
V
-) as high as
OUT
V
REF
REF
OUT
V
CA3338, CA3338A
EE
+
-
of D/A varies.
12
13
11
10
10-16
Short
82
delays. The V
well bypassed as near the chip as possible.
“Glitch” energy is defined as a spurious voltage that occurs as
the output is changed from one voltage to another. In a binary
input converter, it is usually highest at the most significant bit
transition (7F
measured by displaying the output as the input code alter-
nates around that point. The “glitch” energy is the area
between the actual output display and an ideal one LSB step
voltage (subtracting negative area from positive), at either the
positive or negative-going step. It is usually expressed in pV/s.
The CA3338 uses a modified R2R ladder, where the 3 most
significant bits drive a bar graph decoder and 7 equally
weighted resistors. This makes the “glitch” energy at each
scale transition (1F
essentially equal, and far less than the MSB transition would
otherwise display.
For the purpose of comparison to other converters, the output
should be resistively divided to 1V full scale. Figure 5 shows a
typical hook-up for checking “glitch” energy or settling time.
The settling time of the A/D is mainly a function of the output
resistance (approximately 160 in parallel with the load resis-
tance) and the load plus internal chip capacitance. Both
“glitch” energy and settling time measurements require very
good circuit and probe grounding: a probe tip connector such
as Tektronix part number 131-0258-00 is recommended.
R1
75
18
+
+
HEX
REF
R1
62
160
130
R2
75
+2.5V
-2.5V
+5V
+ (and V
to 80
HEX
R2
HEX
to 20
REF
for an 8 bit device), and can be
PROBE TIP
OR BNC
CONNECTOR
N/C
R3
93
75
50
- if bipolar) terminal should be
HEX
, 3F
HEX
ANALOG
GROUND
V
to 40
OUT (P-P)
0 79V
1V
1V
1V
R3
HEX
REMOTE
V
OUT
, etc.)
1
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8