CA3338 Intersil Corporation, CA3338 Datasheet - Page 5

• Manufacturer Part Number: CA3338
• Description: CMOS Video Speed/ 8-Bit/ 50 MSPS/ R2R D/A Converters
• Manufacturer: Intersil Corporation

Latch Operation
Data is fed from input to output while LE is low: LE should be
tied low for non-clocked operation.
Non-clocked operation or changing data while LE is low is
not recommended for applications requiring low output
“glitch” energy: there is no guarantee of the simultaneous
changing of input data or the equal propagation delay of all
bits through the converter. Several parameters are given if
the converter is to be used in either of these modes: t
gives the delay from the input changing to the output chang-
ing (10%), while t
(referred to LE rising edge) needed to latch data. See
Figures 1 and 2.
Clocked operation is needed for low “glitch” energy use.
Data must meet the given t
edge, and the t
delay to the output changing, t
falling edge.
There is no need for a square wave LE clock; LE must only
meet the minimum t
tion. Generally, output timing (desired accuracy of settling)
sets the upper limit of usable clock frequency.
Output Structure
The latches feed data to a row of high current CMOS drivers,
which in turn feed a modified R2R ladder network.
The “N” channel (pull down) transistor of each driver plus the
bottom “2R” resistor are returned to V
scale reference. The “P” channel (pull up) transistor of each
driver is returned to V
FIGURE 2. DATA AND LATCH ENABLE TO OUTPUT TIMING
INPUT DATA
ENABLE
LATCH
INPUT
DATA
VOLTAGE
ENABLE
OUTPUT
t
SU1
LATCH
FIGURE 1. DATA TO LATCH ENABLE TIMING
LATCHED
H
SU2
hold time from the LE rising edge. The
W
REF
and t
pulse width for successful latch opera-
t
FEEDTHROUGH
D2
90%
+, the (+) full-scale reference.
t
D1
H
SU1
DATA
t
give the set up and hold times
W
D1
set up time to the LE falling
10%
, is now referred to the LE
t
r
t
S
REF
t
H
- this is the (-) full-
LATCHED
1
/
CA3338, CA3338A
t
2
SU2
1
LSB
/
2
LSB
D2
10-15
In unipolar operation, V
analog ground, but may be raised above ground (see specifi-
cations). There is substantial code dependent current that
flows from V
specifications), so V
to ground.
In bipolar operation, V
voltage (the maximum voltage rating to V
observed). V
output drivers, must be returned to a point at least as nega-
tive as V
decreases when the bipolar mode is used.
Static Characteristics
The ideal 8-bit D/A would have an output equal to V
an input code of 00
equal to 255/256 of V
code of FF HEX (full scale output). The difference between the
ideal and actual values of these two parameters are the OFF-
SET and GAIN errors, respectively; see Figure 3.
If the code into an 8-bit D/A is changed by 1 count, the output
should change by 1/255 (full scale output - zero scale output). A
deviation from this step size is a differential linearity error, see
Figure 4. Note that the error is expressed in fractions of the
ideal step size (usually called an LSB). Also note that if the (-)
differential linearity error is less (in absolute numbers) than 1
LSB, the device is monotonic. (The output will always increase
for increasing code or decrease for decreasing code).
If the code into an 8-bit D/A is at any value, say “N”, the output
voltage should be N/255 of the full scale output (referred to the
zero scale output). Any deviation from that output is an integral
linearity error, usually expressed in LSBs. See Figure 4.
Note that OFFSET and GAIN errors do not affect integral
linearity, as the linearity is referenced to actual zero and full
scale outputs, not ideal. Absolute accuracy would have to
also take these errors into account.
255/256
254/256
253/256
3/256
2/256
1/256
FIGURE 3. D/A OFFSET AND GAIN ERROR
0
REF
00
EE
REF
(SHOWN +)
INPUT CODE IN HEXADECIMAL (COMP = LOW)
-. Note that the maximum clocking speed
OFFSET
ERROR
, which supplies the gate potential for the
+ to V
01
REF
HEX
= IDEAL TRANSFER CURVE
= ACTUAL TRANSFER CURVE
REF
REF
02
REF
- should have a low impedance path
REF
(zero scale output), and an output
+ (referred to V
- would be returned to a negative
- would typically be returned to
- (see V
03
REF
REF
+ input current in
FD
GAIN ERROR
-) with an input
(SHOWN -)
DD
FE
REF
must be
FF
- with