CA3338 Intersil Corporation, CA3338 Datasheet - Page 4

• Manufacturer Part Number: CA3338
• Description: CMOS Video Speed/ 8-Bit/ 50 MSPS/ R2R D/A Converters
• Manufacturer: Intersil Corporation

Electrical Specifications
NOTE:
Pin Descriptions
REFERENCE VOLTAGE
V
V
V
SUPPLY VOLTAGE
Static I
Dynamic I
Dynamic I
V
V
DIGITAL INPUTS D0 - D7, LE, COMP
High Level Input Voltage
Low Level Input Voltage
Leakage Current
Capacitance
TEMPERATURE COEFFICIENTS
Output Impedance
1. Parameter not tested. but guaranteed by design or characterization.
REF
REF
REF
DD
EE
PIN
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Rejection
Rejection
+ Range
+ Input Current
- Range
DD
PARAMETER
DD
DD
V
or I
V
NAME
COMP
V
V
V
REF
V
REF
D7
D6
D5
D4
D3
D2
D1
OUT
D
LE
SS
EE
DD
or I
or I
EE
0
+
EE
EE
-
Most Significant Bit
Digital Ground
Least Significant Bit. Input Data Bit
Analog Ground
Reference Voltage Negative Input
Analog Output
Reference Voltage Positive Input
Data Complement Control input. Active High
Latch Enable Input. Active Low
Digital Power Supply, +5V
(+) Full Scale, Note 1
(-) Full Scale, Note 1
V
LE = Low, D0 - D7 = High
LE = Low, D0 - D7 = Low
V
V
50kHz Sine Wave Applied
50kHz Sine Wave Applied
Note 1
Note 1
REF
OUT
OUT
T
Unless Otherwise Specified (Continued)
A
DESCRIPTION
= 25
+ = 6V, V
= 10MHz, 0V to 5V Square Wave
= 10MHz, 2.5V Square Wave
TEST CONDITIONS
o
C, V
DD
DD
Input
Data
Bits
(High = True)
= 6V
= 5V, V
CA3338, CA3338A
REF
+ = 4.608V, V
10-14
Digital Signal Path
The digital inputs (LE, COMP, and D0 - D7) are of TTL
compatible HCT High Speed CMOS design: the loading is
essentially capacitive and the logic threshold is typically
1.5V.
The 8 data bits, D0 (weighted 2
are applied to Exclusive OR gates (see Functional Diagram).
The COMP (data complement) control provides the second
input to the gates: if COMP is high, the data bits will be
inverted as they pass through.
The input data and the LE (latch enable) signals are next
applied to a level shifter. The inputs, operating between the
levels of V
and V
will be discussed under bipolar operation. All further logic
elements except the output drivers operate from the V
and V
The upper 3 bits of data, D5 through D7, are input to a 3-to-7
line bar graph encoder. The encoder outputs and D0 through
D4 are applied to a feedthrough latch, which is controlled by
LE (latch enable).
V
SS
REF
MIN
V
EE
EE
= V
2
EE
-
-
-
-
-
-
-
-
-
-
-
- + 3
. V
supplies.
EE
DD
EE
= V
and V
optionally at ground or at a negative voltage,
REF
- = GND, LE Clocked at 20MHz, R
SS
TYP
100
200
40
20
25
3
1
5
-
-
-
-
-
1
, are shifted to operate between V
0
) through D7 (weighted 2
V
REF
MAX
V
220
100
0.8
50
DD
-
-
-
-
-
-
-
5
+ - 3
ppm/
L
UNITS
mV/V
mV/V
mA
mA
mA
pF
V
V
V
V
A
1 M ,
A
A
o
C
DD
DD
7
),