MT9196AS Zarlink Semiconductor, Inc., MT9196AS Datasheet - Page 22

• Manufacturer Part Number: MT9196AS
• Description: Integrated Digital Phone Circuit (IDPC)
• Manufacturer: Zarlink Semiconductor, Inc.

MT9196
Note: Bits marked "-" are reserved bits and should be written with logic "0".
7-156
C-Channel Register
D-Channel Register
Loopback Register
Loop1
Loop2
Notes:
Micro-port access to the ST-BUS C-Channel information
1)
2)
3)
When high, the selected B-channel in ST-BUS mode (i.e., B2/B1 and Transmit and Receive Path selections) or the strobed
B-channel in SSI mode is looped back from Din to Dout through the FDI block. The C & D channels (ST-BUS mode) are not
looped back. When low, the device operates normally.
When high, Loop1 is invoked with the transmit and receive digital gain adjustment being included. This loopback should only
be used if PCM resides in the B-channel. If a data pattern is being looped back then use Loop1 or use Loop2 after ensuring
that the transmit and receive digital gain registers are set to 0dB (address 19h). When low, the device operates normally.
D7
do not enable Loop1 and Loop2 simultaneously.
both loopback modes add an extra frame delay to the data transmission.
ensure that all other bits of address 17h are written logic low when accessing this register.
B7
7
7
7
-
D6
B6
6
6
6
-
Loop2
D5
B5
5
5
5
Loop1
D4
B4
4
4
4
D3
B3
3
3
3
-
D2
B2
2
2
2
-
D1
B1
1
1
1
-
ADDRESS = 17h WRITE/READ VERIFY
D0
B0
0
0
0
-
ADDRESS = 14h WRITE/READ
ADDRESS = 15h WRITE/READ
ADDRESS = 16h RESERVED
Power Reset Value
Power Reset Value
Power Reset Value
XX00 XXXX
1111 1111
1111 1111