MT9196AS Zarlink Semiconductor, Inc., MT9196AS Datasheet - Page 14

• Manufacturer Part Number: MT9196AS
• Description: Integrated Digital Phone Circuit (IDPC)
• Manufacturer: Zarlink Semiconductor, Inc.

MT9196
bit first, on DSTo. On power-up reset (PWRST) or
software reset (RST, address 0Fh) all C-Channel bits
default to logic high. Receive C-Channel data (DSTi)
is always routed to the read register regardless of
this control bit's logic state.
When low, data transmission is halted and this
timeslot is tri-stated on DSTo.
B1-Channel and B2-Channel
Channels 2 and 3 are the B1 and B2 channels,
respectively. B-channel PCM associated with the
Digital Gain, Filter/CODEC and transducer audio
paths is selected on an independent basis for the
transmit and receive paths. For example, the transmit
path may use the B1 channel while the receive path
uses the B2 channel. Although not normally
required, this flexibility is allowed.
For ST-BUS mode the configuration of bits 0 to 3, at
address 12h, defines both the source of transmit
audio
configuration of this register permits selection of only
one transmit B-Channel at a time. If no valid transmit
path has been selected, via the Transmit Path
Selection Register, for a particular B-Channel then
that timeslot output on DSTo is tri-stated.
When a valid receive path has been selected, via the
Receive Path Selection Register (address 13h), the
active receive B-Channel is governed by the state of
the B2/B1 control bit in Control register 1 (address
0Eh).
Refer to the Path Selection section for detailed
information.
SSI Mode
The SSI BUS consists of input and output serial data
streams named Din and Dout respectively, a Clock
input signal (CLOCKin), and a framing strobe input
(STB). A 4.096 MHz master clock, at CLOCKin, is
required for SSI operation if the bit clock is less than
512 kHz. The timing requirements for SSI are shown
in Figures 13 and 14.
In SSI mode the IDPC supports only B-Channel
operation. The internal C and D Channel registers
used in ST-BUS mode are not functional for SSI
operation. The control bit B2/B1, as described in the
ST-BUS section, is ignored since the B-Channel
timeslot is defined by the input STB strobe. Hence, in
SSI mode transmit and receive B-Channel data are
always in the channel defined by the STB input.
7-148
and
the
B-Channel
destination.
The
The data strobe input STB determines the 8-bit
timeslot used by the device for both transmit and
receive data. This is an active high signal with an 8
kHz repetition rate.
SSI operation is separated into two categories based
upon the serial data rate. If the bit clock is 512 kHz or
greater then the bit clock is used directly by the
internal
operation. In this case, the bit clock is connected
directly to the CLOCKin pin while XSTAL2 is left
unconnected. If the available bit clock rate is 128 kHz
or 256 kHz then a 4096 kHz master clock is required
to derive clocks for the internal IDPC functions. If this
clock is available externally then it may be applied
directly to the CLOCKin pin. If a 4096 kHz clock is
not available then provision is made to connect a
4096 kHz crystal across the CLOCKin and XSTAL2
pins as shown in Figure 9. The oscillator circuit has
been designed to require an external feedback
resistor and load capacitors. This configuration
allows normal ST-BUS operation and synchronous
SSI operation with clocks which are not loaded by
these extra components.
Applications where the bit clock rate is below 512
kHz are designated as asynchronous. The IDPC will
generate and re-align its internal clocks to allow
operation when the external master and bit clocks
are asynchronous.
clock is not connected to the IDPC. Control bits
Asynch/Synch, CSL1 and CSL0 in FDI Control
Register (address 10h) are used to program the bit
rates as shown in Table 3.
CLOCKin
IDPC
Figure 9 - External Crystal Circuit
XSTL2
(for asynchronous operation)
functions
In this case, the external bit
33 pF
33 pF
allowing
4096 kHz
Nominal
synchronous
100 k