MT9044AP1 Zarlink Semiconductor, Inc., MT9044AP1 Datasheet - Page 4

• Manufacturer Part Number: MT9044AP1
• Description: Framer: Framer Circuit: T1/E1/OC3 System Synchronizer
• Manufacturer: Zarlink Semiconductor, Inc.

Pin Description (continued)
PLCC
Pin #
19
20
21
22
24
25
26
27
29
30
32
33
34
35
36
MQFP
Pin #
13
14
15
16
18
19
20
21
23
24
26
27
28
29
30
HOLDOVER Holdover (CMOS Output). This output goes to a logic high whenever the digital
Name
ACKo
LOS2
LOS1
C19o
C16o
ACKi
TDO
MS2
C2o
C4o
C8o
C6o
GTo
GTi
Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at
2.048Mb/s.
Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at
2.048Mb/s and 4.096Mb/s.
Clock 19.44MHz (CMOS Output). This output is used in OC3/STS3 applications.
Analog PLL Clock Input (CMOS Input). This input clock is a reference for an
internal analog PLL. This pin is internally pulled down to VSS.
Analog PLL Clock Output (CMOS Output). This output clock is generated by
the internal analog PLL.
Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at
8.192Mb/s.
Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation
with a 16.384MHz clock.
Clock 6.312 Mhz (CMOS Output). This output is used for DS2 applications.
PLL goes into holdover mode.
Guard Time (Schmitt Input). This input is used by the MT9044 state machine in
both Manual and Automatic modes. The signal at this pin affects the state
changes between Primary Holdover Mode and Primary Normal Mode, and
Primary Holdover Mode and Secondary Normal Mode. The logic level at this input
is gated in by the rising edge of F8o. See Tables 4 and 5.
Guard Time (CMOS Output). The LOS1 input is gated by the rising edge of F8o,
buffered and output on GTo. This pin is typically used to drive the GTi input
through an RC circuit.
Secondary Reference Loss (TTL Input). This input is normally connected to the
loss of signal (LOS) output signal of a Line Interface Unit (LIU). When high, the
SEC reference signal is lost or invalid. LOS2, along with the LOS1 and GTi inputs
control the MT9044 state machine when operating in Automatic Control. The logic
level at this input is gated in by the rising edge of F8o. This pin is internally pulled
down to VSS.
Primary Reference Loss (TTL Input). Typically, external equipment applies a
logic high to this input when the PRI reference signal is lost or invalid. The logic
level at this input is gated in by the rising edge of F8o. See LOS2 description. This
pin is internally pulled down to VSS.
Test Serial Data Out (TTL Output). JTAG serial data is output on this pin on the
falling edge of TCK. This pin is held in high impedance state when JTAG scan is
not enabled.
Mode/Control Select 2 (TTL Input). This input, in conjunction with MS1,
determines the device’s mode (Automatic or Manual) and state (Normal, Holdover
or Freerun) of operation. The logic level at this input is gated in by the rising edge
of F8o. See Table 3.
Zarlink Semiconductor Inc.
MT9044
4
Description
Data Sheet